Package Chip Dielectric Layer Etching Prevention

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Solution Overview

Problem

Etching the oxide layer of package chips can easily cause a channel to be defined between adjacent pads, leading to short circuits due to corrosion by acidic or alkaline solutions used in the etching process.

Innovation Solution

A method involving a dielectric layer of silicon dioxide covering the chip's surface, preventing oxidation and eliminating the need for etching, which includes forming through holes in the dielectric layer for electroplating conductive posts to connect pads without exposing them to corrosive solutions.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If the oxide layer on pads is etched to expose conductive surface, then the pads can be properly connected, but channels may be defined between adjacent pads causing short circuits

Engineering Contradiction:
Improvepad connection accuracyVSAvoidshort circuit prevention
Core Design Contradiction:
Manufacturing precisionVSReliability

Solution Approach 1:

The patent applies preliminary action by forming a protective film on the pad surfaces before etching the oxide layer. This protective film is selectively removed only in the pad areas during etching, preventing channels from forming between adjacent pads while still allowing proper pad connection. The protective film acts as a pre-established barrier that guides the etching process to occur only where intended.

Inventive Principle:
Principle #10Preliminary action

2Reliability

If oxide layer is left on pads for protection, then pads are protected from oxidation, but etching is required later which risks creating channels between pads

Engineering Contradiction:
Improvepad oxidation protectionVSAvoidetching process complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent introduces an intermediary protective film that mediates between the oxide layer and the etching process. This protective film allows the oxide layer to remain on the pads for protection while providing a controlled interface for etching. The protective film is selectively removed to expose pad areas for connection, eliminating the need for complex selective etching processes and reducing the risk of channel formation.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Ease of manufacture

If traditional etching process is used to expose pads, then pad connectivity is achieved, but manufacturing yield decreases due to channel formation between adjacent pads

Engineering Contradiction:
Improvepad exposure processVSAvoidmanufacturing yield
Core Design Contradiction:
Ease of manufactureVSProductivity

Solution Approach 1:

The patent applies preliminary action by pre-forming a protective film pattern that defines the exact areas where etching should occur. This preliminary protective film structure guides the etching process to expose only the intended pad areas while automatically preventing channel formation between adjacent pads. This approach maintains ease of manufacture through a straightforward etching process while significantly improving manufacturing yield by eliminating the channel formation problem.

Inventive Principle:
Principle #10Preliminary action

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach enhances the air tightness of package chips, prevents short circuits, reduces manufacturing costs, and allows for precise definition of through holes without damaging the pads, improving yield and reliability.

Implementation Method 1

coating silicon dioxide on a surface of a side of the chip... a dielectric layer, covering the surface of the chip where the plurality of pads are disposed... the dielectric layer comprises silicon dioxide

Methodology Applied
Scientific EffectOxidation prevention: Dielectric

Implementation Method 2

performing electroplating on the chip that defines the through hole, and forming a conductive post in the through hole

Methodology Applied
Scientific EffectElectroplating: Electroplating

Data Source

PatentUS20220246557A1Package chip and method of manufacturing the same, rewiring package chip and method of manufacturing the same
Publication Date: 2022.08.04 SHENNAN CIRCUITS
  • US20220246557A1 patent drawing
  • US20220246557A1 patent drawing
  • US20220246557A1 patent drawing

AI summary

A method of manufacturing a package chip, a package chip, a method of manufacturing a rewiring package chip, and a rewiring package chip are provided. Since a dielectric layer covering a surface of a chip and conductive surfaces of pads does not need to be partially removed by etching, air tightness of the package chip may be improved to prevent the pads from being oxidized by the air, and at the same time, an etching operation may not be performed to etch the pads. In this way, the pads may be prevented from being etched, and a short circuit, which is caused by the surface of the chip being corroded by the etching solution, may be prevented.