Semiconductor Package Structure With Conductive Pillars for 3D Co-Planarity
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Solution Overview
Problem
The semiconductor industry faces challenges in achieving stable packaging techniques for semiconductor dies that support miniaturization, higher speed, greater bandwidth, lower power consumption, and reduced latency, as existing methods struggle to maintain integration density and reliability in 3D packaging and 3DIC devices.
Innovation Solution
A package structure is fabricated using a carrier with a release layer, dielectric layer, metallization pattern, redistribution circuit structure, conductive pillars, and a wiring substrate, where the conductive pillars maintain a predetermined distance between the redistribution circuit structure and the wiring substrate, enhancing co-planarity and reliability through an insulating encapsulation and de-bonding process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional packaging techniques are used for semiconductor dies, then existing manufacturing methods can be maintained, but integration density and reliability deteriorate in 3D packaging and 3DIC devices
Solution Approach 1:
The packaging process is segmented into distinct phases: forming the redistribution circuit structure on a carrier, mounting the wiring substrate, and then de-bonding the carrier. This segmentation allows each phase to be optimized independently, enabling high integration density while maintaining reliability through controlled processing steps.
Solution Approach 2:
The carrier is used to preliminarily support and position the redistribution circuit structure and wiring substrate before final assembly. This preliminary action enables precise alignment and stable positioning during manufacturing, which is critical for maintaining reliability in complex 3D packaging configurations.
2Productivity
If miniaturization is pursued to increase integration density, then more components can be integrated, but packaging stability deteriorates
Solution Approach 1:
The carrier acts as an intermediary substrate that provides mechanical support and stability during the packaging process. It enables the assembly of miniaturized components with high precision while maintaining overall structural stability, allowing miniaturization to proceed without compromising packaging stability.
Solution Approach 2:
The patent transitions from planar 2D packaging to three-dimensional 3D packaging with vertical stacking of the redistribution circuit structure and wiring substrate. This dimensional change increases integration density by utilizing the third dimension while the carrier provides the necessary mechanical stability for this complex 3D configuration.
3Productivity
If 3D packaging and 3DIC devices are implemented to increase integration density, then productivity improves, but manufacturing precision deteriorates
Solution Approach 1:
The carrier is used to preliminarily position and align both the redistribution circuit structure and wiring substrate with high precision before final assembly. This preliminary positioning action ensures that when the structures are mounted and subsequently de-bonded, the alignment precision is maintained despite the complexity of 3D packaging operations.
Data Source
AI summary
A package structure including a redistribution circuit structure, a wiring substrate, a conductive pillar and a solder material is provided. The redistribution circuit structure has a first surface and a second surface opposite to the first surface and includes a first insulating layer and a first redistribution pattern in the insulating layer. The first redistribution pattern comprises a first contact pad disposed at the first surface. The wiring substrate is disposed opposite the first surface of the redistribution circuit structure and includes a second insulating layer and a second redistribution pattern in the second insulating layer. The second redistribution pattern comprises a second contact pad. The conductive pillar is disposed between the first contact pad and the second contact pad. The solder material disposed between the conductive pillar and the second contact pad.