Semiconductor Package Connecting Module Reducing Height

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Solution Overview

Problem

The challenge in semiconductor package technology is to reduce the height of package structures while maintaining lower manufacturing costs, especially for multi-functional semiconductor packages that require higher integration and smaller volume.

Innovation Solution

A package structure incorporating a redistribution structure, die, connecting modules with conductive bars embedded in a protection layer, and multiple insulating encapsulants is used, where the connecting modules serve as vertical connecting features, reducing the package height and eliminating the need for additional carriers or thicker copper pillars.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Length of stationary object

If conventional package structures with additional carriers or thicker copper pillars are used, then vertical connection and electrical connectivity are achieved, but the package height increases and manufacturing cost increases

Engineering Contradiction:
Improvepackage heightVSAvoidmanufacturing cost
Core Design Contradiction:
Length of stationary objectVSEase of manufacture

Solution Approach 1:

The patent merges the carrier function and vertical connection function into a single integrated structure. The connecting module combines the carrier substrate with conductive bars and connection interfaces, eliminating the need for separate carrier and connection components, thereby reducing package height and manufacturing cost

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The connecting module serves multiple functions simultaneously: it acts as a carrier substrate, provides vertical electrical connection through conductive bars, enables mechanical support, and facilitates thermal management. This multi-functionality replaces multiple separate components with a single universal module

Inventive Principle:
Principle #6Universality (Multi-functionality)

2Productivity

If chip stacking is implemented to increase capacity, then data storage and processing capability improve, but package height increases

Engineering Contradiction:
Improvedata capacityVSAvoidpackage height
Core Design Contradiction:
ProductivityVSLength of stationary object

Solution Approach 1:

The patent transitions from horizontal expansion to vertical stacking by implementing multi-layer chip architecture. Chips are stacked in the vertical dimension with connecting modules providing inter-layer electrical connections, enabling increased data capacity without proportional increase in package footprint

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

Multiple chips are nested vertically within the package structure, with each chip layer containing functional elements. The connecting modules are nested between chip layers, providing electrical interconnection while maintaining compact vertical integration

Inventive Principle:
Principle #7Nested doll (Nesting)

Data Source

PatentUS10950593B2Package structure including at least one connecting module and manufacturing method thereof
Publication Date: 2021.03.16 POWERTECH TECHNOLOGY INC
  • US10950593B2 patent drawing
  • US10950593B2 patent drawing
  • US10950593B2 patent drawing

AI summary

A package structure including a redistribution structure, a die, at least one connecting module, a first insulating encapsulant, a chip stack, and a second insulating encapsulant. The die is disposed on and electrically connected to the redistribution structure. The connecting module is disposed on the redistribution structure. The connecting module has a protection layer and a plurality of conductive bars. The conductive bars are embedded in the protection layer. The protection layer includes a plurality of openings corresponding to the conductive bars. The first insulating encapsulant encapsulates the die and the connecting module. The chip stack is disposed on the first insulating encapsulant and the die. The chip stack is electrically connected to the connecting module. The second insulating encapsulant encapsulates the chip stack.