Semiconductor Package Connecting Module and Redistribution Layer Integration
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Solution Overview
Problem
Current wafer-level packaging methods for semiconductor devices face challenges in efficiently integrating semiconductor dies, surface mount devices, and antenna elements while maintaining a compact form factor and high electrical connectivity.
Innovation Solution
The method involves a multi-step process using a carrier with a debond layer, redistribution layers, through vias, UBM patterns, and insulating encapsulation to securely attach and connect semiconductor dies, surface mount devices, and antenna elements, with debonding and planarization steps to ensure stable adhesion and exposure for further connections.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If wafer-level packaging methods are used to integrate semiconductor devices, then manufacturing efficiency is improved, but integration complexity of multiple components increases
Solution Approach 1:
The packaging process is divided into distinct stages: wafer-level packaging for initial integration, followed by substrate-level packaging for additional components. This segmentation allows efficient bulk processing at wafer level while enabling complex multi-component integration at substrate level, resolving the contradiction between manufacturing efficiency and integration complexity
Solution Approach 2:
The patent transitions from two-dimensional wafer-level integration to three-dimensional substrate-level packaging. By stacking components vertically on the substrate and using multiple packaging layers, the design achieves high-density integration of semiconductor dies, surface mount devices, and antenna elements while maintaining wafer-level manufacturing efficiency
2Volume of moving object
If compact form factor is achieved through integrated packaging, then device size is reduced, but adhesion stability of components deteriorates
Solution Approach 1:
Adhesion promoters and underfill materials are applied in advance before component placement. The substrate is pre-prepared with adhesive layers and the wafer is pre-aligned with registration marks, ensuring stable adhesion from the outset. This preliminary action prevents adhesion failures that would otherwise occur in compact designs where components are closely spaced
Solution Approach 2:
The patent uses composite packaging materials including multi-layer substrates with different CTE (coefficient of thermal expansion) layers, adhesive promoters, and encapsulants with tailored mechanical properties. These composite materials provide both the compact form factor and the adhesion stability needed to maintain component integrity in small packages
3Reliability
If high electrical connectivity is achieved through multiple connection points, then signal transmission quality is improved, but manufacturing process complexity increases
Solution Approach 1:
The substrate serves multiple functions simultaneously: it provides mechanical support, electrical interconnection through traces and vias, thermal management pathways, and alignment registration features. This multi-functionality reduces manufacturing process complexity by consolidating multiple requirements into a single component rather than requiring separate processes for each function
Solution Approach 2:
The patent introduces intermediate connection structures including redistribution layers (RDL), underfill materials, and encapsulants that mediate between the wafer-level and substrate-level packaging stages. These intermediaries provide robust electrical pathways and mechanical coupling, ensuring high signal transmission quality while simplifying the overall manufacturing process through modular integration
Data Source
AI summary
A package structure includes a first redistribution layer, a second redistribution layer, at least one semiconductor chip, an insulating encapsulation, a protection layer, and at least one connecting module. The at least one semiconductor chip is located between and electrically connected to the first redistribution layer and the second redistribution layer. The insulating encapsulation encapsulates the at least one semiconductor chip. The protection layer is disposed on and partially covers the first redistribution layer, wherein the first redistribution layer is located between the at least one semiconductor chip and the protection layer. The at least one connecting module connects to the first redistribution layer and is electrically connected to the at least one semiconductor chip through the first redistribution layer, wherein the at least one connecting module comprises a plurality of pins, and the at least one connecting module is mounted onto the first redistribution layer by the protection layer and is accessibly exposed by the protection layer.