Package Structure With Coplanar Encapsulant Surface
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional quad flat package (QFP) structures using leadframes as chip carriers are limited by their lead quantity and layout, which restricts compatibility and system-integrating capabilities, and face challenges with heat dissipation and melt-flashing during encapsulation.
Innovation Solution
A package structure integrating a leadframe with a circuit substrate, featuring leads with inner and outer portions, a heatsink for heat dissipation, and a coplanar encapsulant surface to prevent melt-flashing, along with bonding wires and a cushion block to enhance compatibility and system integration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a conventional QFP structure with leadframe is used, then the packaging is compact and production cost is low, but the lead quantity and layout are limited, reducing compatibility and system-integrating capability
Solution Approach 1:
The patent merges the leadframe and circuit substrate into a single integrated carrier structure. The leadframe serves as both the mechanical support and the electrical interconnection system, while the circuit substrate provides additional routing capacity. This combination increases lead quantity and layout flexibility without proportionally increasing overall package complexity.
Solution Approach 2:
The integrated carrier structure serves multiple functions simultaneously: mechanical support, electrical interconnection, signal routing, and heat dissipation. The circuit substrate not only provides additional leads but also acts as a platform for mounting multiple chips and other components, enhancing system-integrating capability.
2Quantity of substance
If more leads are added to meet increasing contact requirements, then system-integrating capability improves, but the leadframe layout becomes more complex and difficult to manufacture
Solution Approach 1:
The patent transitions from a two-dimensional leadframe layout to a three-dimensional integrated structure where leads are distributed across multiple layers of the circuit substrate. This allows additional leads to be added without increasing the planar footprint or complicating the stamping process, as leads can be routed through vertical interconnections.
3Volume of stationary object
If a compact package design is used, then volume is minimized and production cost is reduced, but heat dissipation capability is limited
Solution Approach 1:
The circuit substrate acts as an intermediary thermal management component between the chips and the package exterior. It provides thermal vias and conductive pathways that efficiently conduct heat away from the chips while maintaining the compact package volume, thus decoupling the volume-heat dissipation trade-off.
4Reliability
If encapsulant is formed to protect internal components, then reliability improves, but melt-flashing phenomenon occurs during forming, reducing production yield
Solution Approach 1:
The patent implements preliminary actions during the encapsulant formation process, including optimizing mold temperature, injection pressure, and rate to prevent melt-flashing before it occurs. The integrated carrier structure also provides better dimensional stability during molding, reducing the likelihood of flash formation.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution provides improved compatibility, system-integrating capability, effective heat dissipation, and prevents melt-flashing, ensuring better production yields and device connectivity.
Implementation Method 1
a heatsink embedded inside the encapsulant and contacting the inner lead portions of the leads
Implementation Method 2
each first bonding wire is electrically connected to the corresponding inner lead portion and the circuit substrate, and each second bonding wire is electrically connected between the chip and the circuit substrate
Data Source
AI summary
A package structure including a circuit substrate, at least a chip, leads and an encapsulant is provided. The circuit substrate has a first surface, a second surface opposite to the first surface, and contacts disposed on the first surface. The chip is disposed on the second surface of the circuit substrate and electrically connected to the circuit substrate. The leads are disposed on the periphery of the second surface and surround the chip. Each lead has an inner lead portion and an outer lead portion and is electrically connected to the circuit substrate via the inner lead portion. The encapsulant encapsulates the circuit substrate, the chip and the inner lead portion and exposes the first surface of the circuit substrate and the outer lead portion, wherein the upper surface of the encapsulant and the first surface of the circuit substrate are coplanar with each other.