Semiconductor Package Corner Die Layout Against Molding Delamination
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Solution Overview
Problem
Semiconductor packages experience molding delamination at corners due to increased substrate contraction force, particularly when semiconductor dies with equal height to the insulating encapsulant are located at package corners.
Innovation Solution
Reduce the thickness of semiconductor dies at package corners and embed them in an insulating encapsulant, which covers their backside surfaces, counteracting substrate contraction force and reducing molding delamination risk.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If semiconductor dies with equal height to insulating encapsulant are used at package corners, then package structure simplicity is maintained, but molding delamination occurs due to increased substrate contraction force
Solution Approach 1:
The patent applies local quality by differentiating the thickness of semiconductor dies based on their location within the package. Corner dies are made thinner than central dies, creating a spatial variation in structural properties. This localized modification reduces substrate contraction force at corners where molding delamination is most likely to occur, while maintaining full thickness at central locations for optimal electrical performance.
Solution Approach 2:
The patent changes the thickness parameter of semiconductor dies at package corners to resolve the contradiction. By reducing the thickness of corner dies relative to central dies, the substrate contraction force at vulnerable corner locations is decreased, thereby preventing molding delamination while maintaining overall package structural integrity.
2Reliability
If thinner semiconductor dies are used at package corners, then molding stress is reduced, but manufacturing precision requirements increase
Solution Approach 1:
The patent segments the semiconductor die population into two distinct groups based on location: corner dies and central dies. This segmentation allows for differentiated thickness specifications, where corner dies are manufactured with reduced thickness to minimize molding stress, while central dies maintain standard thickness for optimal electrical characteristics.
Solution Approach 2:
The patent implements local quality by assigning different thickness specifications to different spatial locations within the package. Corner locations receive thinner dies to reduce molding stress, while central locations receive full-thickness dies for electrical performance, thereby managing manufacturing precision requirements through location-based differentiation.
Data Source
AI summary
A package structure includes first semiconductor dies, second semiconductor dies, electrical connectors, an interconnection layer and an underfill structure. The first semiconductor dies are embedded in an insulating encapsulant, wherein backside surfaces of the first semiconductor dies are revealed by the insulating encapsulant. The second semiconductor dies are embedded in corners of the insulating encapsulant, wherein backside surfaces of the second semiconductor dies are covered by the insulating encapsulant. The electrical connectors are disposed on the first semiconductor dies and the second semiconductor dies. The interconnection layer is disposed on the insulating encapsulant and electrically connected to the first semiconductor dies and the second semiconductor dies through the electrical connectors. The underfill structure is disposed in between the first semiconductor dies, the second semiconductor dies and the interconnection layer, and laterally surrounding the electrical connectors.