Semiconductor Package Structure for CTE Mismatch and Warpage Control

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Solution Overview

Problem

The semiconductor industry faces challenges in forming smaller packages for integrated circuits due to thermal expansion coefficient (CTE) mismatches, leading to warpage and structural integrity issues during the packaging process.

Innovation Solution

A method involving the use of a warpage control material with controlled thermal expansion properties, combined with a protection material and encapsulant, to manage CTE mismatches and reduce warpage in integrated circuit packages, along with a redistribution structure to facilitate electrical connections.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Area of moving object

If smaller packages are used to reduce area, then area is reduced, but thermal expansion coefficient mismatches cause warpage and structural integrity issues

Engineering Contradiction:
Improvepackage areaVSAvoidstructural integrity
Core Design Contradiction:
Area of moving objectVSStability of the object's composition

Solution Approach 1:

The patent introduces a redistribution layer as an intermediary structure between the semiconductor die and the package substrate. This redistribution layer serves as a buffer that absorbs and distributes thermal expansion stresses, preventing direct transmission of CTE mismatch forces to the die and package structure, thereby maintaining structural integrity in smaller packages

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The patent modifies the physical and material parameters of the package structure by using multi-layer redistribution layers with different material compositions and thicknesses. These parameter changes allow the structure to better accommodate thermal expansion differences while maintaining mechanical stability in reduced-size packages

Inventive Principle:
Principle #35Parameter changes

2Quantity of substance

If continuous reductions in minimum feature size are made to improve integration density, then integration density is improved, but manufacturing complexity and precision requirements increase

Engineering Contradiction:
Improveintegration densityVSAvoidfeature size precision
Core Design Contradiction:
Quantity of substanceVSManufacturing precision

Solution Approach 1:

The patent divides the interconnection structure into multiple segmented layers (first redistribution layer, second redistribution layer, third redistribution layer) rather than using single-layer traces. This segmentation allows each layer to be manufactured with relaxed precision requirements while achieving the same or better overall routing capability, thus supporting higher integration density without proportionally increasing manufacturing precision demands

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent transitions from two-dimensional planar routing to three-dimensional multi-layer routing. By utilizing vertical stacking of redistribution layers, the patent achieves higher integration density by routing signals in multiple dimensions, reducing the precision burden on any single layer while maintaining overall system performance

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

3Reliability

If redistribution circuit structures are formed to facilitate connections, then electrical connectivity is improved, but manufacturing process complexity increases

Engineering Contradiction:
Improveelectrical connectivityVSAvoidmanufacturing process complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent designs the redistribution layers to serve multiple functions simultaneously: electrical interconnection, mechanical stress distribution, and thermal management. This multi-functionality reduces the need for separate specialized structures, thereby improving electrical connectivity without proportionally increasing manufacturing process complexity

Inventive Principle:
Principle #6Universality (Multi-functionality)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The solution effectively reduces warpage and enhances structural integrity of semiconductor packages, ensuring reliable electrical connections and improved manufacturing yield.

Implementation Method 1

A method involving the use of a warpage control material with controlled thermal expansion properties, combined with a protection material and encapsulant, to manage CTE mismatches and reduce warpage in integrated circuit packages

Methodology Applied
Scientific EffectThermal expansion: Thermal Expansion

Data Source

PatentUS12564054B2Package structure
Publication Date: 2026.02.24 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US12564054B2 patent drawing
  • US12564054B2 patent drawing
  • US12564054B2 patent drawing

AI summary

A package structure includes a die, an encapsulant laterally encapsulating the die, a warpage control material disposed over the die, and a protection material disposed over the encapsulant and around the warpage control material. A coefficient of thermal expansion of the protection material is less than a coefficient of thermal expansion of the encapsulant.