Semiconductor Package Dam Structure for Thermal Stress Cracks
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Solution Overview
Problem
Existing semiconductor package structures face issues with thermal expansion mismatch, leading to stress and potential cracks due to material incompatibilities, which can cause failure.
Innovation Solution
Incorporating a dam structure within the redistribution layer between semiconductor dies, which reduces stress and enhances the strength of the package by minimizing the stress coupling effect, and integrating the dam structure with the redistribution layer formation to avoid additional processing steps.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If different materials are used in the semiconductor package structure, then functional requirements are met, but thermal expansion mismatch introduces stress and may cause cracks
Solution Approach 1:
The patent divides the package structure into distinct layers including a substrate, semiconductor die, and molding compound, with the dam structure creating a segmentation between different material regions. This segmentation allows each layer to accommodate its own thermal expansion independently, reducing stress transmission across material interfaces.
Solution Approach 2:
The dam structure acts as an intermediary element between different materials with different thermal expansion coefficients. It serves as a stress-absorbing interface that mediates the thermal expansion mismatch, preventing direct stress transmission that would cause cracks in the semiconductor die or other components.
2Reliability
If a dam structure is added to reduce stress, then crack resistance improves, but device complexity increases
Solution Approach 1:
The dam structure is merged with the molding compound material, using the same or compatible materials for both the dam structure and the surrounding molding compound. This integration reduces the number of discrete components and simplifies the manufacturing process while still providing the stress-reducing functionality.
Solution Approach 2:
The molding compound serves multiple functions: it provides structural support, electrical insulation, and environmental protection, while also forming the dam structure that reduces thermal stress. This multi-functionality reduces the need for additional specialized components.
3Productivity
If a dam structure is integrated with the redistribution layer formation, then manufacturing efficiency improves, but manufacturing precision requirements increase
Solution Approach 1:
The dam structure is formed preliminarily during the redistribution layer formation process, before the final package assembly. By establishing the dam structure early in the manufacturing sequence, subsequent processing steps can proceed without additional alignment or positioning operations, improving overall manufacturing efficiency.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The dam structure effectively mitigates stress-induced cracks and enhances the structural integrity of the semiconductor package, ensuring reliable performance by reducing thermal expansion mismatch-related issues.
Implementation Method 1
a thermal expansion mismatch between different materials may introduce stress
Data Source
Figure 1A~1B
Figure 1C~1D
Figure 1E~1F
AI summary
A semiconductor package structure includes a redistribution layer, a first semiconductor die, a second semiconductor die, a molding material, and a dam structure. The redistribution layer has a first surface and a second surface opposite the first surface. The first semiconductor die and the second semiconductor die are disposed over the first surface of the redistribution layer. The molding material is arranged between the first semiconductor die and the second semiconductor die. The dam structure is disposed in the redistribution layer. The dam structure is arranged under the molding material between the first semiconductor die and the second semiconductor die.