Package Dielectric Void Structure for BGA Pad Impedance Control
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Solution Overview
Problem
Large ball grid array (BGA) pads in semiconductor devices cause significant capacitance, leading to signal reflections and losses due to high capacitance, which existing solutions like metal voiding or inductor-like structures either reduce local metal density or complicate package design.
Innovation Solution
Incorporating dielectric voids or dielectric foam with a low dielectric constant around pads to reduce capacitance, thereby improving signal integrity and package reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If large metal voids are created in multiple metal planes above and below the pads, then capacitance of the pads is decreased, but local metal density is significantly reduced and manufacturing and reliability risks increase
Solution Approach 1:
The patent applies local quality by creating voids specifically in the dielectric material directly beneath high-capacitance pads rather than using extensive metal voiding across multiple planes. This localized approach reduces capacitance where needed while preserving metal density in other areas, thereby maintaining manufacturing reliability and signal integrity without the risks associated with large-scale metal removal.
2Quantity of substance
If metal voiding is implemented in multiple layers, then capacitance is reduced, but routing requirements prevent the ability to implement metal voiding in some layers
Solution Approach 1:
The patent extracts the dielectric material beneath the pads to create voids, removing the source of capacitance without interfering with metal routing in other layers. This extraction approach reduces pad capacitance while leaving the metal planes and routing structures intact, thereby maintaining routing flexibility and avoiding the conflicts that arise when attempting to implement metal voiding across multiple constrained layers.
3Quantity of substance
If spiral inductor like structures with extra routings are used to increase inductance adjacent to the pad, then inductance is increased, but the package design becomes very complicated and back-side layers are significantly congested
Solution Approach 1:
Instead of adding complex inductor structures to increase inductance, the patent inverts the approach by reducing capacitance through dielectric voiding beneath the pads. This inversion simplifies the package design by eliminating the need for spiral inductors and extra routings, thereby reducing congestion in back-side layers while achieving impedance control through capacitance reduction rather than inductance enhancement.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The use of dielectric voids or foam reduces capacitance, minimizes signal reflections, and enhances manufacturing reliability by maintaining metal density and simplifying package design.
Implementation Method 1
dielectric voids or dielectric foam with a low dielectric constant around pads to reduce capacitance
Data Source
AI summary
Embodiments disclosed herein include electronic packages and methods of forming such packages. In an embodiment, an electronic package comprises a first buildup layer and a second buildup layer over the first buildup layer. In an embodiment, a void is disposed through the second buildup layer. In an embodiment the electronic package further comprises a first pad over the second buildup layer. In an embodiment, the first pad covers the void.