Semiconductor Package Dummy Bump Layout for Coplanarity Control
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Solution Overview
Problem
In semiconductor packaging, maintaining uniformity and coplanarity of bumps, especially in the peripheral regions, is challenging as dimensions and pitches are scaled down, leading to issues with bump array uniformity and reliability.
Innovation Solution
The introduction of dummy bumps surrounding conducting bumps in the same process improves uniformity and coplanarity, with dummy bumps being electrically floating and not connected to semiconductor dies, while conducting bumps provide electrical connections, and an underfill encapsulates both, guiding its extension and enhancing bonding reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If bump dimensions and pitches are scaled down to increase integration density, then productivity and device functionality are improved, but manufacturing precision and reliability of bump array uniformity deteriorate
Solution Approach 1:
The patent applies local quality by introducing dummy bumps specifically in peripheral regions where coplanarity issues occur, rather than uniformly across the entire bump array. This localized addition of non-conductive bumps addresses the specific manufacturing precision problem in critical areas while maintaining the scaled-down dimensions and high integration density of the functional conducting bumps in the core region.
2Reliability
If conducting bumps are formed with high precision to ensure electrical connection reliability, then bonding reliability is improved, but device complexity and manufacturing cost increase
Solution Approach 1:
The patent applies homogeneity by forming both conducting bumps and dummy bumps using the same manufacturing process steps (electroplating, patterning, etching). This unified approach ensures that both bump types achieve consistent quality and coplanarity without requiring separate complex manufacturing lines, thereby maintaining bonding reliability while avoiding increased device complexity.
Solution Approach 2:
The patent applies copying by creating dummy bumps that replicate the physical structure and formation process of conducting bumps, but without the conductive material fill. This copying approach allows the dummy bumps to serve as structural references that improve the coplanarity of conducting bumps through the shared manufacturing process, enhancing bonding reliability without adding significant manufacturing complexity.
Data Source
AI summary
A semiconductor package and a manufacturing method for the semiconductor package are provided. The semiconductor package includes a redistribution layer, a semiconductor die, conducting connectors, dummy bumps and an underfill. The semiconductor die is disposed on a top surface of the redistribution layer and electrically connected with the redistribution layer. The conducting connectors are disposed between the semiconductor die and the redistribution layer, and are physically and electrically connected with the semiconductor die and the redistribution layer. The dummy bumps are disposed on the top surface of the redistribution layer, beside the conducting connectors and under the semiconductor die. The underfill is disposed between the semiconductor die and the redistribution layer and sandwiched between the dummy bumps and the semiconductor die. The dummy bumps are electrically floating. The dummy bumps are in contact with the underfill without contacting the semiconductor die.