Semiconductor Package Edge Reinforcement for Warpage and Crack Transfer

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Solution Overview

Problem

Semiconductor packages experience warpage due to thermal expansion differences among components, leading to non-wet defects and reduced reliability.

Innovation Solution

Incorporation of warpage reduction members with controlled thermal expansion properties on the substrate edges and surfaces to manage and control package warpage, using materials like adhesive films or resins with fillers to distribute stress and prevent crack transfer.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If warpage reduction members are added to control package warpage, then mounting reliability is improved, but device complexity increases

Engineering Contradiction:
Improvemounting reliabilityVSAvoidpackage structure complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

Warpage reduction members are selectively positioned at specific locations on the substrate, such as corner regions or edge regions, rather than uniformly across the entire substrate. This localized approach controls warpage effectively while minimizing the increase in device complexity by only adding components where they are most needed for warpage control.

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The warpage reduction members are constructed using composite material structures, such as adhesive films combined with filler particles (e.g., ceramic fillers like alumina or silica). These composite materials provide the necessary mechanical properties for warpage control while maintaining a relatively simple overall package structure, thus improving reliability without excessive complexity increase.

Inventive Principle:
Principle #40Composite materials

2Reliability

If warpage reduction members are positioned at edge regions of the substrate, then crack transfer to package interior is minimized, but manufacturing precision requirements increase

Engineering Contradiction:
Improvecrack resistanceVSAvoidmember positioning precision
Core Design Contradiction:
ReliabilityVSManufacturing precision

Solution Approach 1:

The warpage reduction members are divided into multiple discrete units positioned at different edge regions or corners of the substrate. This segmentation allows for more flexible positioning and reduces the overall manufacturing precision requirement for each individual member, while collectively providing effective crack transfer prevention at the package edges.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Instead of requiring precise positioning of warpage reduction members across the entire substrate perimeter, the invention applies members at key critical locations such as corner regions or specific edge portions. This partial action approach is sufficient to prevent crack transfer to the package interior while significantly reducing the manufacturing precision requirements compared to complete perimeter coverage.

Inventive Principle:
Principle #16Partial or excessive action

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

Enhances mounting reliability by minimizing warpage and crack propagation, improving connectivity and overall package performance.

Implementation Method 1

a difference in a coefficient of thermal expansion (CTE) between components in the semiconductor package... warpage phenomenon in which a semiconductor package is bent or twisted frequently occurs

Methodology Applied
Scientific EffectThermal expansion: Thermal Expansion

Implementation Method 2

using materials like adhesive films or resins with fillers to distribute stress and prevent crack transfer

Methodology Applied
Scientific EffectStress distribution:

Data Source

PatentUS20250210542A1Semiconductor package
Publication Date: 2025.06.26 SAMSUNG ELECTRONICS CO LTD
  • US20250210542A1 patent drawing
  • US20250210542A1 patent drawing
  • US20250210542A1 patent drawing

AI summary

A semiconductor package includes a substrate including an inner layer wiring structure including an insulating layer and a wiring layer, a first protective layer on a first surface of the inner layer wiring structure, a second protective layer on a second surface of the inner layer wiring structure that is opposite to the first surface of the inner layer wiring structure, and a first warpage reduction member and a second warpage reduction member on the first protective layer, a semiconductor chip above the first protective layer and connected to the substrate, and a molding material encapsulating the semiconductor chip, where the first warpage reduction member is on a first side surface of the substrate, and the second warpage reduction member is on a second side surface of the substrate, the second side surface being opposite to the first side surface.