Semiconductor Package Edge Interconnects Without an Interposer

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Solution Overview

Problem

The integration density of semiconductor components increases, making it challenging to connect integrated circuit dies through interposers alone.

Innovation Solution

The implementation of edge interconnect features, which are conductive lines extending through sealing rings and into scribe line regions, allowing direct connections between neighboring integrated circuit dies without the need for an interposer.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If interposers are used to connect integrated circuit dies, then connections between dies can be established, but device complexity and production costs increase

Engineering Contradiction:
Improveconnection reliabilityVSAvoidpackage complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent extracts and eliminates the interposer component from the package structure. By forming conductive lines directly through the substrate to connect adjacent dies, the interposer is removed entirely, reducing device complexity while maintaining connection functionality between integrated circuit dies

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The patent merges the substrate's conductive interconnect structure with the die attachment process. The conductive lines are formed within the substrate itself, combining the substrate's mechanical support function with the electrical interconnection function that previously required a separate interposer

Inventive Principle:
Principle #5Merging (Combining)

2Productivity

If integration density increases, then more components can be integrated, but connecting dies through interposers becomes more challenging

Engineering Contradiction:
Improveintegration densityVSAvoidinterposer complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent segments the interconnection approach by forming individual conductive lines through the substrate at specific locations between adjacent dies. This segmented approach allows flexible routing and connection establishment that adapts to high integration density layouts without requiring a complex overall interposer structure

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent transitions from a planar interposer-based connection approach to a vertical through-substrate conductive line approach. By extending conductors through the substrate thickness dimension, direct electrical paths are created between dies without requiring lateral interposer routing, enabling higher integration density

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

3Reliability

If conventional die connections are used, then dies can be connected, but tolerance to cutting operations is reduced

Engineering Contradiction:
Improveconnection reliabilityVSAvoidcutting tolerance
Core Design Contradiction:
ReliabilityVSManufacturing precision

Solution Approach 1:

The patent incorporates conductive lines that extend beyond the die boundaries into the substrate, creating a buffer zone that absorbs cutting variations. This beforehand cushioning ensures that even if cutting positions vary, the conductive connections remain intact and functional

Inventive Principle:
Principle #11Beforehand cushioning (Prior cushioning)

Data Source

PatentUS12374637B2Semiconductor packages and methods for forming the same
Publication Date: 2025.07.29 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US12374637B2 patent drawing
  • US12374637B2 patent drawing
  • US12374637B2 patent drawing

AI summary

Embodiments of the present disclosure provide an integrated circuit die having edge interconnect features. The edge interconnect features may be conductive lines extending through sealing rings and into scribe line regions. In some embodiments, heterogeneous integrated circuit dies with edge interconnect features are fabricated on the same substrate. Edge interconnect features of the neighboring integrated circuit dies are connected to each other and provide direct connections between the integrated circuit dies without going through an interposer.