Semiconductor Package Edge Layer Layout to Prevent Protective Film Lifting
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Solution Overview
Problem
The existing methods of fabricating semiconductor packages face issues such as particle introduction and crack generation due to reduced adhesive strength or lifting of protective films during the removal of carrier substrates, leading to reduced production yield and reliability at the wafer level.
Innovation Solution
A method involving the formation of conductive patterns and protective films with controlled peel strengths is employed, where a dummy conductive layer is maintained on the edge area to enhance the peeling force of the protective film, thereby reducing defects during the dicing process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a protective film is formed on the back surface of the wafer substrate to protect it during processing, then the wafer substrate is protected from damage, but the adhesive strength of the protective film may be reduced due to difference in peeling force during carrier substrate removal, causing film lifting or particle introduction
Solution Approach 1:
The patent applies different photoresist patterns with different peel strengths to different regions of the wafer substrate. The first photoresist pattern is applied to the chip area where strong adhesion is needed, while the second photoresist pattern is applied to the edge area where controlled peeling is desired. This local differentiation allows the protective film to maintain adhesion where needed while enabling clean removal where not needed, resolving the contradiction between protective adhesion and controlled release.
Solution Approach 2:
The patent segments the wafer substrate into two distinct regions: chip area and edge area. By forming separate photoresist patterns on these segmented regions with different adhesive properties, the system can simultaneously achieve strong protective adhesion on the chip area and controlled peeling on the edge area, thereby preventing film lifting and particle introduction while maintaining reliability.
2Ease of manufacture
If the carrier substrate is removed after forming the protective film, then the front surface processing is complete, but the difference in peeling force may reduce adhesive strength of the protective film, leading to cracks or reduced production yield
Solution Approach 1:
The patent uses locally differentiated photoresist patterns to control the peeling behavior during carrier substrate removal. The first photoresist pattern on the chip area maintains strong adhesion to prevent protective film damage, while the second photoresist pattern on the edge area allows controlled peeling. This local quality differentiation enables easy carrier removal without compromising production yield.
Solution Approach 2:
The photoresist patterns act as an intermediary layer between the protective film and the carrier substrate. By controlling the adhesive properties of this intermediary layer through regional differentiation, the patent enables controlled carrier substrate removal that prevents protective film damage, thereby maintaining high production yield while facilitating ease of manufacture.
3Reliability
If photoresist patterns are formed on both chip area and edge area, then selective peeling control is achieved, but the process complexity increases with multiple photoresist formation steps
Solution Approach 1:
The patent segments the photoresist formation process into two distinct patterns applied to different regions. While this increases process steps, it provides precise control over peeling forces in different areas, achieving reliable selective peeling control that prevents film lifting and maintains production yield, justifying the increased complexity.
Solution Approach 2:
The patent applies different photoresist patterns with different adhesive properties to different regions of the wafer. This local quality approach allows precise control of peeling forces where needed, achieving reliable selective peeling control that balances the increased process complexity with significant improvements in manufacturing reliability.
Data Source
AI summary
A method of manufacturing a semiconductor package includes providing a wafer substrate including a first a chip area and an edge area; forming first and second conductive layers on the wafer substrate; forming a photoresist pattern, including openings, on the second conductive layer, wherein the photoresist pattern includes a first photoresist pattern on the chip area and a second photoresist pattern on the edge area; forming conductive patterns within the openings; removing the first photoresist pattern from the photoresist pattern, and portions of the first and second conductive layers overlapping with the first photoresist pattern; removing the second photoresist pattern from the photoresist pattern, and a portion of the second conductive layer overlapping the second photoresist pattern, such that a portion of the first conductive layer on the edge area is exposed; and forming a protective film such that the protective film is on the conductive patterns.