Semiconductor Package Edge Layout for Mold Shelf Heat Transfer
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Solution Overview
Problem
Advanced semiconductor package architectures face issues due to the singulation process, which introduces mold shelves with low thermal conductivity, leading to reduced thermal design performance, increased yield losses, and reliability concerns with high-thermal conductivity mold materials.
Innovation Solution
Implementing semiconductor packages with dummy silicon regions that replace mold shelves, enhancing thermal conductivity and process yield by positioning these regions at the peripheral edges of composite dies, ensuring they are coplanar with the dies' surfaces, thereby improving heat transfer during thermal compression bonding.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If the singulation process is used to cut the silicon wafer into final products, then the manufacturing process is completed, but mold shelves are introduced with low thermal conductivity, reducing thermal design performance
Solution Approach 1:
The patent extracts and removes the mold shelf from the package structure by designing the singulation cut to occur within the dummy silicon region rather than through the molded encapsulant. This eliminates the low-thermal-conductivity mold shelf that would otherwise be present at the package edges, thereby improving thermal performance while maintaining the manufacturing process.
Solution Approach 2:
The patent introduces dummy silicon regions with high thermal conductivity specifically at the peripheral edges of the composite die where mold shelves would normally form. This local modification creates a thermal conduction path at the edges without affecting the overall package structure or requiring changes to the main manufacturing process.
2Temperature
If high-thermal conductivity mold materials are used, then thermal conductivity is improved, but reliability issues increase due to higher process temperatures and flux activity
Solution Approach 1:
The patent introduces dummy silicon regions as intermediary high-thermal-conductivity structures that perform the thermal conduction function without requiring the entire mold material to have high thermal conductivity. This allows localized thermal management at the edges where it is most needed, while the bulk mold material can remain standard and reliable.
3Power
If the bond head peak temperature is increased, then thermal compression bonding effectiveness is improved, but larger temperature gradients in the substrate occur, leading to excessive substrate expansion and non-uniform solder melting
Solution Approach 1:
The patent applies thermal enhancement locally at the peripheral edges through dummy silicon regions rather than increasing the overall bond head temperature. This localized approach provides additional thermal conduction where needed at the edges without creating large temperature gradients across the entire substrate, thereby maintaining bonding effectiveness while avoiding substrate expansion and solder melting issues.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution increases thermal conductivity, expands the process window, and enhances manufacturing yield without increasing costs, addressing the limitations of existing packaging solutions.
Implementation Method 1
enhancing thermal conductivity and process yield by positioning these regions at the peripheral edges of composite dies, ensuring they are coplanar with the dies' surfaces, thereby improving heat transfer during thermal compression bonding
Implementation Method 2
during the TCB bonding of the composite die to the substrate, the corner/edge bumps of the first-level interconnects (FLIs) typically have a much lower temperature. Such FLI corner/edge bumps, therefore, may not even melt in order to form a good joint due to the mold shelf
Data Source
AI summary
Embodiments include semiconductor packages and a method to form such semiconductor packages. A semiconductor package includes a plurality of dies on a substrate, and an encapsulation layer over the substrate. The encapsulation layer surrounds the dies. The semiconductor package also includes a plurality of dummy silicon regions on the substrate. The dummy silicon regions surround the dies and encapsulation layer. The plurality of dummy silicon regions are positioned on two or more edges of the substrate. The dummy silicon regions have a top surface substantially coplanar to a top surface of the dies. The dummy silicon regions include materials that include silicon, metals, or highly-thermal conductive materials. The materials have a thermal conductivity of approximately 120 W/mK or greater, or is equal to or greater than the thermal conductivity of silicon. An underfill layer surrounds the substrate and the dies, where the encapsulation layer surrounds portions of the underfill layer.