Semiconductor Package ESD Protection via Merged Redistribution Lines
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Solution Overview
Problem
Semiconductor packages are vulnerable to overvoltage or undervoltage conditions, such as electrostatic discharge (ESD), which can damage electronic circuits and affect their operation, and existing protection circuits are inadequate in addressing these issues effectively.
Innovation Solution
A package structure incorporating a semiconductor device, through-vias, dielectric layers, and a second molding compound, with redistribution lines that include an ESD-protection feature or a metal-insulator-metal (MIM) feature, providing protection against ESD and enhancing the reliability of the semiconductor device.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional packaging structures are used, then manufacturing simplicity is maintained, but the semiconductor device is vulnerable to ESD damage and voltage fluctuations
Solution Approach 1:
The patent combines ESD protection functionality with the redistribution line structure by integrating an ESD-protection layer into the packaging structure. The ESD-protection layer is formed over the semiconductor device and extends into the molding compound, merging the protection function with the existing interconnection structure rather than adding a separate protection system.
Solution Approach 2:
The redistribution line structure serves multiple functions: electrical interconnection between layers and ESD protection. The ESD-protection layer integrated into the redistribution line provides both signal routing and voltage surge protection, making the structure multi-functional and reducing the need for separate protection circuits.
2Reliability
If ESD protection features are integrated into redistribution lines, then protection effectiveness is improved, but manufacturing complexity increases
Solution Approach 1:
The ESD-protection layer is formed over the semiconductor device before the molding compound is applied, establishing the protection structure in advance. This preliminary formation allows the protection layer to be integrated into subsequent manufacturing steps without requiring additional complex processes.
Solution Approach 2:
The ESD-protection layer extends into the molding compound beyond the device boundaries, changing the spatial parameters of the protection structure. This extension allows the same layer to serve both as an interconnection element and an ESD protection element, achieving multiple functions without proportionally increasing manufacturing complexity.
Data Source
AI summary
The present disclosure relates to a package structure. The package structure includes a semiconductor device, a first molding compound, a through-via, first and second dielectric layers, and a second molding compound in contact with a sidewall of the first dielectric layer. The first molding compound is in contact with a sidewall of the semiconductor device. The through-via is formed in the first molding compound and electrically connected to the semiconductor device. The first and second dielectric layers are formed at upper and lower sides of the semiconductor device. The at least one redistribution line is formed in the first dielectric layer and electrically connected to the semiconductor device and the through-via. The second molding compound is in contact with a sidewall of the first dielectric layer. The at least one redistribution line comprises an ESD-protection feature or a MIM (metal-insulator-metal) feature.