Electronic Package Frame Structure for Warpage Control

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Solution Overview

Problem

Conventional semiconductor packages face warpage issues due to thermal expansion mismatches, which require large dummy blocks that occupy space and hinder miniaturization and increase manufacturing costs.

Innovation Solution

A semiconductor package design featuring a frame body embedded within the packaging layer that disperses thermal stress without contacting the wiring structure or covering electronic components, allowing for other components to be arranged around the chip without increasing the package size.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Stability of the object's composition

If dummy blocks are arranged around the semiconductor chip to reduce warpage, then warpage is reduced, but the surface area occupied increases, leaving no space for other electronic components

Engineering Contradiction:
Improvewarpage reductionVSAvoidsurface area occupied
Core Design Contradiction:
Stability of the object's compositionVSArea of stationary object

Solution Approach 1:

The dummy block is segmented into a frame body structure with multiple legs distributed around the semiconductor chip. Instead of a single large dummy block, the support function is divided into multiple smaller legs positioned at strategic locations, reducing the continuous surface area occupation while maintaining warpage control through distributed support points.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The frame body legs are positioned at specific locations around the semiconductor chip where support is most needed, rather than uniformly distributing material across the entire surface. This localized approach provides warpage control only where thermal stress is concentrated, freeing up other areas for electronic components.

Inventive Principle:
Principle #3Local quality

2Area of stationary object

If the size of the packaging substrate is increased to arrange required wiring layers, then space for wiring is increased, but manufacturing costs increase and miniaturization demand is not met

Engineering Contradiction:
Improvewiring spaceVSAvoidmanufacturing cost
Core Design Contradiction:
Area of stationary objectVSEase of manufacture

Solution Approach 1:

The wiring and electronic components are arranged in a three-dimensional configuration utilizing vertical space above the substrate. The frame body structure allows wiring to be routed through and around the legs, enabling complex wiring patterns without increasing the substrate's planar footprint, thus maintaining miniaturization while providing sufficient wiring space.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

3Stability of the object's composition

If a frame body is embedded in the packaging layer to disperse thermal stress, then warpage is prevented, but the structure complexity increases

Engineering Contradiction:
Improvethermal stress dispersionVSAvoidstructure complexity
Core Design Contradiction:
Stability of the object's compositionVSDevice complexity

Solution Approach 1:

The frame body serves multiple functions simultaneously: it provides mechanical support to prevent warpage, acts as a thermal stress dispersion structure, and creates pathways for wiring routing. The same structural element performs support, thermal management, and spatial organization functions, reducing the need for separate components and thereby limiting the increase in overall structural complexity.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This design effectively prevents warpage during thermal cycles, enabling miniaturization and reducing manufacturing costs by allowing required wirings to be arranged on the surface without enlarging the package size.

Implementation Method 1

a mismatch between the coefficients of thermal expansion (CTE) of the semiconductor chip 11 and the packaging layer would easily result in non-uniform thermal stress, causing the packaging layer 14 to warp during thermal cycles

Methodology Applied
Scientific EffectThermal stress: Thermal Expansion

Data Source

PatentUS12057409B2Electronic package and manufacturing method thereof
Publication Date: 2024.08.06 SILICONWARE PRECISION IND CO LTD
  • US12057409B2 patent drawing
  • US12057409B2 patent drawing
  • US12057409B2 patent drawing

AI summary

An electronic package and a manufacturing method of the electronic package are provided, in which an electronic component is arranged on a wiring structure and covered with a packaging layer, and a frame body that does not contact the wiring structure nor cover the electronic component is embedded in the packaging layer.