Semiconductor Package Guiding Patterns for Void-Free Encapsulation
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Solution Overview
Problem
The semiconductor industry faces challenges in achieving smaller, more efficient packaging techniques for semiconductor dies due to limitations in miniaturization, higher speed, greater bandwidth, lower power consumption, and reduced latency, particularly in the integration and encapsulation processes.
Innovation Solution
The implementation of a redistribution circuit structure with guiding patterns that control the flow of encapsulation material to minimize voids and enhance encapsulation efficiency, including dot patterns, guiding trenches, and retarding strips, which facilitate the encapsulation process without increasing fabrication costs and allow for efficient electrical connections.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional encapsulation processes are used, then fabrication costs are reduced, but void formation increases and encapsulation efficiency deteriorates
Solution Approach 1:
Guiding patterns are formed on the substrate before encapsulation material is applied. These pre-formed patterns create controlled pathways that direct the flow of encapsulation material, ensuring complete coverage and minimizing void formation before the encapsulation process completes.
Solution Approach 2:
The guiding patterns act as an intermediary structure between the substrate and the encapsulation material. These patterns, formed from conductive or non-conductive materials, mediate the flow and distribution of encapsulation material to achieve uniform coverage while preventing void formation.
2Productivity
If miniaturization is pursued to increase integration density, then component size is reduced, but packaging complexity and difficulty increase
Solution Approach 1:
The substrate surface is segmented into multiple regions with different guiding patterns (conductive regions, non-conductive regions, trenches, strips) that control encapsulation material flow in different areas. This segmentation allows complex multi-component packages to be encapsulated systematically despite increased integration density.
Solution Approach 2:
Different regions of the substrate are assigned different local properties through varying guiding pattern configurations. Conductive regions allow material flow, non-conductive regions block flow, trenches create channels, and strips form barriers. This local differentiation enables precise control of encapsulation material distribution across miniaturized, high-density packages.
3Reliability
If guiding patterns are added to control encapsulation flow, then encapsulation efficiency improves, but fabrication complexity increases
Solution Approach 1:
The guiding patterns are formed using existing fabrication processes (photolithography, etching, deposition) that are already part of the semiconductor manufacturing workflow. By merging the guiding pattern formation into the existing fabrication sequence, the additional complexity is minimized while still achieving improved encapsulation efficiency.
Solution Approach 2:
The guiding patterns serve multiple functions: they control encapsulation material flow, provide electrical connectivity in conductive regions, and can serve as structural support. This multi-functionality reduces the need for separate dedicated flow control structures, thereby limiting the increase in fabrication complexity.
Data Source
AI summary
A package structure including a wiring substrate, conductive terminals, an insulating encapsulation, a redistribution circuit structure, guiding patterns and a semiconductor device. The conductive terminals are disposed on a surface of the wiring substrate. The insulating encapsulation laterally encapsulates the wiring substrate and the conductive terminals. The redistribution circuit structure is disposed on the insulating encapsulation and the conductive terminals, and the redistribution circuit structure is electrically connected to the wiring substrate through the conductive terminals. The guiding patterns are disposed between the wiring substrate and the redistribution circuit structure, and the guiding patterns are in contact with and encapsulated by the insulating encapsulation. The semiconductor device is disposed on a top surface of the redistribution circuit structure, and the semiconductor device is electrically connected to the wiring substrate through the redistribution circuit structure and the conductive terminals.