Package-in-Fan-Out Semiconductor Integration via Nested Die Embedding
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Solution Overview
Problem
There is a need to integrate multiple semiconductor dies into a single package with reduced size and manufacturing cost, as existing technologies struggle to achieve smaller, more efficient semiconductor devices with improved packaging and interconnection methods.
Innovation Solution
The method involves creating a semiconductor package with a first interconnect structure, disposing a semiconductor die with a second interconnect structure over the package, depositing an encapsulant, and forming a third interconnect structure to integrate multiple semiconductor dies into a single package-in-fan-out (PI-FOP) configuration, utilizing fan-out packages as a base to reduce size and manufacturing costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If multiple semiconductor dies are integrated into a single package using conventional packaging methods, then the functionality and performance are improved, but the device size and manufacturing cost increase
Solution Approach 1:
The patent embeds a first semiconductor die within an encapsulant of a second semiconductor package, creating a nested configuration where one die is housed inside the package structure of another. This nesting approach allows multiple dies to be integrated into a compact footprint, reducing the overall package volume while maintaining the functionality of multiple semiconductor components.
Solution Approach 2:
The patent transitions from planar packaging to three-dimensional integration by embedding a die within the encapsulant volume rather than placing it on the surface. This vertical stacking and embedding approach utilizes the Z-dimension (height/depth) to accommodate multiple dies, significantly reducing the lateral footprint and overall package size.
2Adaptability or versatility
If multiple semiconductor dies are integrated into a single package using conventional packaging methods, then the functionality and performance are improved, but the manufacturing cost increases
Solution Approach 1:
The patent forms the encapsulant containing the first semiconductor die before attaching the second semiconductor package. This preliminary encapsulation allows the first die to be protected and positioned in advance, enabling subsequent integration steps to be performed more efficiently. The pre-formed encapsulant structure serves as a ready-made housing that simplifies the overall assembly process and reduces manufacturing complexity.
Solution Approach 2:
The patent combines multiple semiconductor dies and their respective interconnect structures into a single integrated package assembly. By merging the first die, its encapsulant, and the second package into one unified structure, the invention eliminates the need for separate packaging processes for each die, thereby reducing overall manufacturing steps and costs while achieving multi-die integration.
3Area of moving object
If smaller semiconductor devices are produced through front-end process improvements, then the die size is reduced, but the packaging and interconnection complexity increases
Solution Approach 1:
The patent embeds a first semiconductor die within an encapsulant of a second semiconductor package, creating a nested configuration where one die is housed inside the package structure of another. This nesting approach allows multiple dies to be integrated into a compact footprint, reducing the overall package volume while maintaining the functionality of multiple semiconductor components.
Solution Approach 2:
The patent employs an encapsulant as an intermediary material that houses the first semiconductor die and provides a structured interface for interconnection with the second package. This encapsulant acts as a mediator that simplifies the interconnection architecture by providing pre-formed contact structures and mechanical support, thereby reducing the overall packaging complexity despite the small die size.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the integration of multiple semiconductor dies into a single package, reducing device size and manufacturing costs, while providing enhanced packaging and interconnection efficiency, suitable for applications in mobile devices and other electronic systems.
Implementation Method 1
depositing an encapsulant over the first semiconductor package and first semiconductor die
Data Source
AI summary
A semiconductor device comprises a first semiconductor package including a first interconnect structure extending over a surface of the first semiconductor package. The first semiconductor package includes an interposer and a second semiconductor die disposed over the interposer. A second encapsulant is deposited over the interposer and second semiconductor die. A first semiconductor die is disposed over the surface of the first semiconductor package. A second interconnect structure extends from the first semiconductor die opposite the first semiconductor package. A first encapsulant is deposited over the first semiconductor package and first semiconductor die. A portion of the first encapsulant over the first interconnect structure and second interconnect structure is removed. A discrete component is disposed on the surface of the first semiconductor package. A build-up interconnect structure is formed over the first semiconductor package and first semiconductor die. The first semiconductor package includes a molded laser package.