3D Package Structure with Embedded Inductor for Footprint Reduction
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Solution Overview
Problem
Current packaging techniques are inadequate for efficiently integrating smaller and more compact electronic devices and semiconductor dies, requiring innovative methods to achieve smaller form factors and improved electrical performance.
Innovation Solution
The method involves using a carrier with a material layer, forming conductive patterns and through interlayer vias, and integrating inductor structures above the chip to reduce footprint and enhance electrical connectivity, utilizing redistribution layers and molding compounds to create compact 3D package structures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If conventional packaging techniques are used, then manufacturing simplicity is maintained, but device size and compactness cannot be sufficiently reduced
Solution Approach 1:
The patent transitions from planar 2D packaging to three-dimensional 3D packaging by stacking multiple layers (substrate, first molding compound, second molding compound) vertically. This dimensional change enables compactness in the Z-direction while maintaining electrical connectivity through through-mold vias that penetrate multiple layers, effectively reducing the package footprint without proportionally increasing complexity.
Solution Approach 2:
The patent implements nesting by placing the chip within the first molding compound, which is itself embedded in the second molding compound. The inductor structure is nested above the chip and electrically connected through vias. This nested arrangement maximizes space utilization and achieves compact packaging by embedding components within each other rather than placing them side-by-side.
2Area of moving object
If component density is increased to reduce footprint, then area is reduced, but electrical performance and power integrity deteriorate
Solution Approach 1:
The patent applies local quality by providing dedicated inductor structures positioned directly above specific chip regions, with through-mold vias creating localized electrical pathways. This localized approach maintains high current density and low inductance in critical areas while reducing overall footprint, thereby preserving electrical performance despite increased component density.
Solution Approach 2:
The patent moves electrical connections from the planar XY-plane to the vertical Z-dimension through through-mold vias that penetrate multiple molding compound layers. This vertical connectivity reduces the horizontal footprint required for electrical paths while maintaining effective electrical performance by shortening current paths and reducing parasitic inductance.
3Volume of moving object
If 3D integration is implemented to achieve compactness, then volume is reduced, but manufacturing complexity increases
Solution Approach 1:
The patent applies preliminary action by forming through-mold vias and inductor structures in the first molding compound before applying the second molding compound. This sequential approach simplifies manufacturing by completing complex via formation and inductor fabrication early in the process while the substrate is accessible, rather than attempting to create these features after final packaging.
Solution Approach 2:
The patent segments the packaging process into distinct stages: forming the first molding compound with embedded vias and inductors, then applying the second molding compound. This segmentation allows each manufacturing step to be optimized independently, reducing overall fabrication complexity despite the 3D integrated structure.
Data Source
AI summary
A package structure has a chip, a molding compound encapsulating the chip and an inductor structure disposed above the chip. A vertical projection of the inductor structure at least partially overlaps with a vertical projection of the chip.