Package Design Interconnect Reuse with Bump Compensation
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Solution Overview
Problem
In electronics manufacturing, concurrent design of integrated circuits and package devices can lead to complex re-designs due to alterations in the integrated circuit layout, requiring manual modifications of package designs, which is time-consuming and inefficient.
Innovation Solution
A computing system implements tools for bump compensation and package design offset correction by exporting and importing route and connectivity data, correlating pin locations, and modifying interconnects to align with new integrated circuit designs, enabling automatic realignment and scaling of interconnects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If manual modification of package design is performed to re-align traces or vias after integrated circuit layout changes, then design adaptability is improved, but productivity deteriorates due to time-consuming manual operations
Solution Approach 1:
The patent replaces manual mechanical operations with automated computational operations. The package design tool automatically performs bump compensation calculations, modifies trace routes, adjusts via locations, and updates net assignments based on input layout changes, eliminating the need for manual drag-and-drop operations while maintaining full design adaptability
Solution Approach 2:
The package design system performs self-service by automatically detecting layout changes, calculating required compensations, and executing design modifications without user intervention. The tool independently manages the entire re-design process including trace realignment, via repositioning, and net name reassignment, allowing the system to adapt to changes autonomously
2Productivity
If automated bump compensation and interconnect realignment is implemented, then productivity is improved, but device complexity increases due to additional computational operations
Solution Approach 1:
The package design tool integrates multiple functions into a single automated workflow: it performs bump compensation calculations, modifies trace routes, repositions vias, updates net assignments, and validates design rules all in one process. This multi-functionality increases productivity while managing complexity by consolidating operations rather than adding separate tools
Solution Approach 2:
The patent introduces an intermediate computational layer that automatically translates layout changes into package design modifications. This intermediary processing layer handles the complexity of coordinate transformations, trace routing calculations, and net mapping, shielding users from complexity while delivering high productivity through automated realignment
Data Source
AI summary
This application discloses a computing system to export route data and connectivity data from a layout design of a package device. The route data describes a structure of an interconnect in the package device. The connectivity data characterizes an electrical interface between a first integrated circuit and the package device in the layout design. The computing system, based on the connectivity data associated with the first integrated circuit, can correlate the route data to pins of a second integrated circuit and identify net names for the route data and the second integrated circuit. The computing system can import the route data and the connectivity data to the layout design, which selectively realigns the route data in the layout design with the pins in the second integrated circuit, and also can allow the computing system to change net names corresponding to the route data connecting to the second integrated circuit.