Semiconductor Package Interface Anchoring Against CTE Delamination
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Solution Overview
Problem
Conventional semiconductor package structures face delamination issues due to coefficient of thermal expansion (CTE) mismatch between the encapsulant and the circuit pattern structure, affecting reliability and performance during thermal processes.
Innovation Solution
Incorporating an anchoring or interlocking structure adjacent to the interface between the encapsulant and the circuit pattern structure to reduce thermal expansion differences, thereby preventing delamination.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If an encapsulant with different material properties is used to cover the circuit pattern structure, then protection and encapsulation are achieved, but delamination occurs due to CTE mismatch during thermal processes
Solution Approach 1:
The interface region is segmented into multiple functional layers including a primer layer and graded intermediate layers with different materials and CTE values. This segmentation allows each layer to handle specific stress conditions, preventing delamination while maintaining protection functionality.
Solution Approach 2:
The interface region is given locally different material properties through graded CTE layers and primer coatings. The material composition varies spatially from the circuit pattern structure side to the encapsulant side, creating a gradient that matches thermal expansion characteristics at each location, thus preventing stress concentration and delamination.
2Reliability
If the CTE mismatch between encapsulant and circuit pattern structure is reduced by material selection, then delamination is prevented, but manufacturing complexity and cost increase
Solution Approach 1:
The CTE parameter is gradually changed across multiple intermediate layers, creating a transition zone. Instead of using a single material with fixed CTE, the patent employs a series of layers with progressively changing CTE values, allowing thermal stress to be distributed and managed through parameter gradation.
Solution Approach 2:
The interface structure uses composite material systems where each layer is composed of specific materials selected for their CTE properties. The graded structure combines multiple materials in a systematic arrangement, creating a composite interface that bridges the CTE gap between the encapsulant and circuit pattern structure.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The anchoring or interlocking structure effectively minimizes delamination caused by CTE mismatch, enhancing the reliability and performance of the semiconductor package structure by maintaining structural integrity during temperature variations.
Implementation Method 1
configured to reduce a difference between a variation of expansion of the encapsulant and a variation of expansion of the circuit pattern structure in an environment of temperature variation
Data Source
AI summary
A semiconductor package structure includes a circuit pattern structure, an encapsulant and an anchoring structure. The encapsulant is disposed on the circuit pattern structure. The anchoring structure is disposed adjacent to an interface between the encapsulant and the circuit pattern structure, and is configured to reduce a difference between a variation of expansion of the encapsulant and a variation of expansion of the circuit pattern structure in an environment of temperature variation.