Package Interface Pi-Network for PCB Impedance Continuity
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Solution Overview
Problem
As digital communication links approach higher symbol rates, impedance mismatches between integrated circuit chips and printed circuit board traces exacerbate signal attenuation and inter-symbol interference, making it difficult for receiving devices to accurately detect symbols, especially when combined with additive noise.
Innovation Solution
The implementation of a packaged integrated circuit interface design that includes a SerDes signal pad connected through a core via and micro-vias to a solder ball, forming a pi-network with parasitic capacitances and inductance to match the expected impedance of the PCB trace, thereby minimizing impedance discontinuity and reducing signal reflections and attenuation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional direct connection methods are used between IC chip and PCB trace, then the connection structure is simple, but impedance mismatch causes severe signal attenuation and ISI at high symbol rates
Solution Approach 1:
The patent introduces a package substrate with a pi-network structure as an intermediary between the IC chip and PCB trace. This intermediate structure includes series inductors and shunt capacitors that actively compensate for impedance mismatches, transforming the simple but mismatched direct connection into a controlled impedance pathway that maintains signal integrity at high symbol rates
Solution Approach 2:
The patent modifies the connection structure by changing its electrical parameters through the pi-network configuration. The series inductors and shunt capacitors are specifically designed to transform the impedance characteristics of the connection, converting a high-impedance discontinuity into a matched impedance pathway that reduces reflections and signal loss
2Manufacturing precision
If impedance matching structures are added to reduce mismatch, then impedance continuity improves, but manufacturing complexity and design difficulty increase
Solution Approach 1:
The patent applies local quality by implementing impedance matching only at the critical interface between the package substrate and PCB trace, rather than throughout the entire connection path. The pi-network is localized to where impedance discontinuity occurs most severely, allowing precise control of impedance characteristics at the problem area while keeping the rest of the structure simple and easy to manufacture
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design effectively reduces impedance discontinuity by over 50% and maintains signal integrity at high symbol rates, as demonstrated by improved time-domain reflectometry and injection loss spectra, ensuring reliable high-bandwidth signal connections.
Implementation Method 1
The core via has a first parasitic capacitance, the solder ball connection is associated with a second parasitic capacitance
Implementation Method 2
the arrangement of micro-vias provides a pi-network inductance that, together with the first and second parasitic capacitances, yields a connection impedance matching an expected impedance of the PCB trace
Data Source
AI summary
An illustrative embodiment of a packaged integrated circuit includes: an integrated circuit chip having a SerDes signal pad; and a package substrate having a core via and an arrangement of micro-vias connecting the SerDes signal pad to an external contact for solder ball connection to a PCB trace. The core via has a first parasitic capacitance, the solder ball connection is associated with a second parasitic capacitance, and the arrangement of micro-vias provides a pi-network inductance that improves connection impedance matching. An illustrative method embodiment includes: obtaining an expected impedance of the PCB trace; determining parasitic capacitances of a core via and a solder ball connection to the PCB trace; minimizing the core via capacitance; calculating a pi-network inductance that improves impedance matching with the PCB trace; and adjusting a micro-via arrangement between the core via and the solder ball connection to provide the pi-network inductance.