Semiconductor Package Joint Structure for Warpage-Stable Soldering
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Solution Overview
Problem
The semiconductor industry faces challenges in packaging technologies due to stress from differences in thermal expansion coefficients between materials, leading to delamination and cold joints in smaller electronic components, which complicates manufacturing and integration.
Innovation Solution
The use of conductive bumps with specific layer structures and dimensions, combined with a reflow process, to form joints between package components, while analyzing warpage characteristics to adjust bump dimensions and solder volume, reduces interconnection defects and stress-related issues.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If smaller electronic components are used to increase integration density, then more components can be integrated into a given area, but stress from thermal expansion differences causes delamination and cold joints
Solution Approach 1:
The patent modifies physical parameters of the joint structure, specifically controlling the thickness of the joint structure (5-20 micrometers) and the dimensions of conductive bumps to optimize stress distribution. By changing these dimensional parameters, the joint structure can accommodate thermal expansion differences while maintaining connection integrity in smaller components.
Solution Approach 2:
The joint structure employs a composite construction with multiple layers including joint filler material and conductive bumps made of different materials with varying thermal expansion coefficients. This composite approach allows the structure to gradiently accommodate thermal stress across different material interfaces, preventing delamination while maintaining electrical connectivity.
2Reliability
If the joint structure thickness is increased to reduce stress, then delamination risk decreases, but the package height increases
Solution Approach 1:
The patent optimizes the thickness parameter of the joint structure to a specific range (5-20 micrometers) that provides sufficient stress distribution to prevent delamination while minimizing the increase in package height. This precise parameter control allows balancing reliability requirements with compact package dimensions.
3Volume of moving object
If conductive bump dimensions are reduced for smaller packages, then package size decreases, but manufacturing precision requirements increase
Solution Approach 1:
The patent establishes specific parameter ranges for conductive bump dimensions and joint structure thickness that enable smaller package volumes while maintaining manufacturability. By defining these parameters within controlled ranges, the invention balances miniaturization goals with achievable manufacturing precision for bump formation and alignment.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively minimizes delamination and cold joints, enhancing the reliability and manufacturing efficiency of semiconductor packages by optimizing the joint structure and warpage management.
Implementation Method 1
a reflow process, to form joints between package components
Implementation Method 2
conductive bumps with specific layer structures and dimensions, combined with a reflow process, to form joints
Implementation Method 3
stress from differences in thermal expansion coefficients between materials
Implementation Method 4
optimizing the joint structure and warpage management
Data Source
AI summary
A semiconductor package includes first and second package components stacked upon and electrically connected to each other, and first and second joint structures. The first package component includes first and second conductive bumps, the second package component includes third and fourth conductive bumps having dimensions greater than those of the first and second conductive bumps. The first joint structure partially covers the first and third conductive bumps. The second joint structure partially covers the second and the fourth conductive bumps. A first angle between a sidewall of the first conductive bump and a tangent line at an end point of a boundary of the first joint structure on the first conductive bump is greater than a second angle between a sidewall of the second conductive bump and a tangent line at an end point of a boundary of the second joint structure on the second conductive bump.