Semiconductor Package Line Routing for Selective Flux Dipping

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Solution Overview

Problem

In semiconductor package manufacturing, existing processes face inefficiencies due to idle tooling and reduced cycle time, as modules often apply different operations to different stages of products, leading to reduced tooling efficiency and potential pollutant residues on electrical terminals that can cause solder ball formation failures.

Innovation Solution

A method and apparatus that include a process line with multiple semiconductor manufacturing portions configured to perform specific operations, such as flux dipping, reflow, and cleaning, allowing for the bypass of certain processes on packaging structures to improve tool efficiency and remove pollutants from electrical terminals, enabling efficient formation of solder balls.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If modules apply different operations to different stages of products in series, then various process steps can be performed, but tooling efficiency is reduced due to idle time

Engineering Contradiction:
Improveprocess operation flexibilityVSAvoidtooling efficiency
Core Design Contradiction:
Adaptability or versatilityVSProductivity

Solution Approach 1:

The process line is divided into multiple independent semiconductor manufacturing portions, each capable of performing specific operations. This segmentation allows different portions to work simultaneously on different packaging structures at different process stages, eliminating idle time and improving overall tooling efficiency while maintaining operational flexibility.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Multiple semiconductor manufacturing portions are combined into a single integrated process line that handles different packaging structures simultaneously. By merging these portions in series, the system achieves both operational versatility and continuous productivity, as each portion contributes to the overall manufacturing flow without creating bottlenecks or idle periods.

Inventive Principle:
Principle #5Merging (Combining)

2Reliability

If flux dipping process is applied to all packaging structures, then electrical terminals are cleaned, but unnecessary processing time is consumed on already cleaned terminals

Engineering Contradiction:
Improvesolder ball formation qualityVSAvoidcycle time
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The flux dipping process is selectively applied only to packaging structures that require it, based on their specific needs. Packaging structures with uncleaned terminals receive the flux dipping treatment, while those with already cleaned terminals bypass this step. This localized approach ensures reliable solder ball formation where needed while minimizing unnecessary processing time.

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The system determines in advance which packaging structures require flux dipping and routes them accordingly before they reach the flux dipping portion. Packaging structures that have already undergone cleaning operations are identified and directed to bypass the flux dipping process, preventing redundant processing and optimizing cycle time.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS11837572B2Apparatus and method for manufacturing semiconductor package structure
Publication Date: 2023.12.05 ADVANCED SEMICON ENG INC
  • US11837572B2 patent drawing
  • US11837572B2 patent drawing
  • US11837572B2 patent drawing

AI summary

An apparatus and method for manufacturing a semiconductor package structure are provided. The method includes: providing a process line comprising a first semiconductor manufacturing portion configured to provide a first operation including a first process step, and a second semiconductor manufacturing portion configured to provide a second operation including a second process step; passing a packaging structure through the second semiconductor manufacturing portion, wherein the second semiconductor manufacturing portion applies the second process step to the packaging structure; passing the packaging structure through the first semiconductor manufacturing portion, wherein the first semiconductor manufacturing portion applies the first process step to the packaging structure; and passing the packaging structure through the second semiconductor manufacturing portion again without applying the second process step thereon.