Package Module Direct Chip-to-Carrier Connection
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Solution Overview
Problem
Conventional packaging methods face challenges such as impedance mismatch, thermal stress, and dimension limitations, which hinder miniaturization and increase the complexity of electrical connections, leading to performance issues and manufacturing difficulties.
Innovation Solution
A package design featuring a carrier with a first chip, a dielectric layer, and a connecting part that allows for a shorter electrical connection path, enabling direct electrical connection between the chip and the carrier or other packages, with flexible layout and improved manufacturing processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If wire bonding method is used to electrically connect chip with carrier, then electrical connection is achieved, but impedance mismatch occurs due to various lengths of gold wires
Solution Approach 1:
The patent extracts the gold wire bonding process and replaces it with a direct conductive connection structure. The connecting part is integrated into the carrier substrate, eliminating the need for separate wire bonding elements and their associated length variations that cause impedance mismatch.
Solution Approach 2:
The patent introduces a connecting part as an intermediary element between the chip and carrier. This connecting part includes a first conductive pattern on the chip, a second conductive pattern on the carrier, and a connecting structure that provides a controlled impedance path, serving as a mediator that ensures consistent electrical characteristics.
2Reliability
If flip chip packaging method is used with bumps, then electrical connection is achieved, but thermal stress and chip damage occur during reflowing and packaging processes
Solution Approach 1:
The patent replaces the reusable bump structure with a disposable-like connecting part that is pre-formed and integrated into the carrier. This connecting part is designed to be applied once during manufacturing and eliminates the need for high-temperature reflow processes that cause thermal stress.
Solution Approach 2:
The patent changes the manufacturing parameters by eliminating the reflow soldering process. Instead of using high-temperature bump formation and reflow, the connecting part is attached using lower-temperature methods, fundamentally changing the thermal parameters of the packaging process to avoid chip damage.
3Reliability
If pin through hole method is used with metal leads, then electrical connection is achieved, but package dimension cannot be easily minimized
Solution Approach 1:
The patent transitions from a three-dimensional pin through hole structure to a planar two-dimensional conductive pattern structure. The connecting part uses conductive patterns on the surface and within the substrate plane rather than vertical pins extending through the entire package thickness, reducing the overall package volume.
Solution Approach 2:
The patent replaces the physical pin structure with a planar conductive pattern copy of the connection function. Instead of using raised metal pins that occupy vertical space, the electrical connection is achieved through conductive traces and patterns that lie flat within the substrate layers, minimizing package height and volume.
4Reliability
If conventional packaging methods are used, then electrical connection is achieved, but manufacturing processes become complex and assembly is difficult
Solution Approach 1:
The patent merges multiple separate manufacturing steps into a single integrated process. The connecting part is designed to be attached in one step that simultaneously establishes both mechanical support and electrical connection, eliminating the need for separate wire bonding or bump formation processes.
Solution Approach 2:
The connecting part serves multiple functions simultaneously: it provides mechanical support for the chip, establishes electrical connection between chip and carrier, and provides a controlled impedance path. This multi-functionality reduces the number of separate components and manufacturing steps required.
Data Source
AI summary
A package includes a carrier, a first chip, a first dielectric layer and at least one first connecting part. The carrier has a first surface and a second surface, and at least one first pad is disposed on the second surface. The first chip is disposed on the first surface. The first dielectric layer is disposed on the first surface and covers the first chip. The first connecting part is disposed in the first dielectric layer and disposed around an edge of the first chip to electrically connect the first chip with the first pad. A package module of the package is also disclosed.