Semiconductor Package Moisture Gap for Cavity Venting Reliability
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Solution Overview
Problem
Moisture retained in sealed cavities between passive components and the package substrate in semiconductor packages can cause reliability issues during thermal processes like re-flow, as existing technologies do not effectively manage moisture escape.
Innovation Solution
Incorporating a moisture passing gap in the top build-up wiring layer of the package substrate, filled with an upper dielectric layer, which is aligned with the cavity to allow moisture escape during thermal processes, maintaining the gap's dimensions smaller than or equal to the passive component to prevent signal integrity disruption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a sealed cavity is formed between the passive component and the top surface of the package substrate, then the passive component is protected and enclosed, but moisture retained in the cavity causes reliability issues during thermal processes
Solution Approach 1:
The top build-up wiring layer is segmented by creating a moisture passing gap that divides the continuous metal plane into separate regions. This gap allows moisture to escape from the cavity while the remaining metal planes maintain electrical connectivity through alternative paths, thus resolving the contradiction between sealing and moisture removal.
Solution Approach 2:
The moisture passing gap acts as an intermediary structure between the sealed cavity and the external environment. It provides a controlled pathway for moisture to escape during thermal processes while maintaining the overall sealed structure, enabling moisture management without compromising the protective enclosure.
2Object-affected harmful factors
If a moisture passing gap is created in the top build-up wiring layer, then moisture can escape from the cavity, but the power or ground plane continuity may be disrupted
Solution Approach 1:
The metal plane is intentionally segmented by the moisture passing gap, but electrical connectivity is maintained through alternative routing paths in the wiring layer. This segmentation allows moisture to pass through the gap while the divided metal regions remain electrically connected via other conductive paths, preventing signal integrity issues.
Solution Approach 2:
The moisture passing gap creates a localized discontinuity in the planar dimension, but the wiring layer compensates by providing three-dimensional connectivity through vertical vias and alternative horizontal paths. This dimensional approach allows moisture to escape in one location while maintaining electrical connectivity through other spatial routes.
3Object-affected harmful factors
If the moisture passing gap is aligned with the cavity, then moisture escape is maximized, but the gap dimensions must be controlled to prevent signal integrity disruption
Solution Approach 1:
The moisture passing gap has localized dimensions that are specifically optimized for moisture escape while minimizing impact on electrical performance. The gap width and length are controlled to provide sufficient moisture ventilation without creating excessive discontinuity in the power or ground plane, achieving local optimization at the gap location while maintaining overall system integrity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The moisture passing gap effectively allows retained moisture to escape, mitigating reliability issues during thermal processes without affecting the signal integrity of the power or ground plane.
Implementation Method 1
moisture retained in the cavity escapes through the moisture passing gap during thermal processes
Data Source
Figure 1
Figure 2
AI summary
A semiconductor package (1) includes a package substrate (100) having a top surface (S1) and an opposing bottom surface (S2). The package substrate (100) includes a top build-up wiring layer (MO) and an upper dielectric layer (110) covering the top build-up wiring layer (MO). A semiconductor device (10) and a passive component (20) are mounted on the top surface (S1) of the package substrate (100) in a side-by-side manner. A molding compound (50) encapsulates the semiconductor device (10) and the passive component (20) on the top surface (S1) of the package substrate (100). A cavity (CA) is disposed between the passive component (20) and the top surface (S1) of the package substrate (100). A moisture passing gap (GP1) is disposed in the top build-up wiring layer (MO) of the package substrate (100).