Semiconductor Package Molding Layer for Thermal Mismatch Control
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Solution Overview
Problem
Semiconductor packages face challenges with thermal expansion mismatch between components, leading to stress, delamination, and warpage, which affect reliability and operational stability.
Innovation Solution
A semiconductor package design featuring a molding layer with a higher coefficient of thermal expansion than the semiconductor die, covering the sidewalls of the interposer substrate and chip stacks, and an under-fill layer with a different thermal expansion coefficient, counterbalancing the thermal expansion differences between the package substrate and semiconductor die to prevent delamination and warpage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional semiconductor package structure is used without a molding layer, then the structure is simpler and easier to manufacture, but thermal expansion mismatch causes stress, delamination, and warpage
Solution Approach 1:
A molding layer is introduced as an intermediary component between the substrate and the semiconductor die. This molding layer has a coefficient of thermal expansion that is higher than that of the semiconductor die, serving as a mediator to counterbalance the thermal expansion mismatch and prevent delamination and warpage during temperature changes.
Solution Approach 2:
The coefficient of thermal expansion of the molding layer is specifically selected to be higher than that of the semiconductor die. By changing the thermal expansion parameter of the molding layer, the overall thermal expansion mismatch in the package structure is compensated, reducing stress and improving reliability.
2Reliability
If a molding layer with higher thermal expansion coefficient is added, then thermal expansion mismatch is counterbalanced and delamination is prevented, but the package structure becomes more complex
Solution Approach 1:
The molding layer is applied locally at specific regions where thermal expansion mismatch causes the most stress. The structure includes a first molding pattern and a second molding pattern that cover critical areas such as the substrate sidewalls and semiconductor chip sidewalls, providing targeted protection without unnecessarily complicating the entire package structure.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The design effectively reduces stress and warpage, enhancing the operating reliability of semiconductor packages by managing thermal expansion mismatches and maintaining structural integrity.
Implementation Method 1
A coefficient of thermal expansion of the first molding pattern is greater than a coefficient of thermal expansion of the semiconductor die. The molding layer is disposed on a bottom surface at the overhang region of the first lower semiconductor chip. A bottom surface of the molding layer is coplanar with a bottom surface of the interposer substrate.
Data Source
AI summary
A semiconductor package includes a first semiconductor chip that has a mount region and an overhang region, a substrate disposed on a bottom surface at the mount region of the first semiconductor chip, and a molding layer disposed on the substrate. The molding layer includes a first molding pattern disposed on a bottom surface at the overhang region of the first semiconductor chip and covering a sidewall of the substrate, and a second molding pattern on the first molding pattern and covering a sidewall of the first semiconductor chip.