Electronic Package Offset Suppression Layer for Chip Alignment
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Solution Overview
Problem
The mismatch in coefficients of thermal expansion between glass substrates and encapsulants in semiconductor packages leads to offsetting of semiconductor chips during high-temperature molding or curing processes, resulting in yield loss.
Innovation Solution
An electronic package is designed with an offset suppression layer made of polyimide material, which is formed on a carrier and has a coefficient of thermal expansion matching that of the encapsulant, thereby suppressing the offset of electronic elements during thermal expansion and contraction.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If high-temperature molding or curing process is performed on the encapsulant, then the encapsulant is properly formed and cured, but the glass substrate expands and contracts due to CTE mismatch, causing the semiconductor chip to offset
Solution Approach 1:
An offset suppression layer is introduced as an intermediary component between the glass substrate and the semiconductor chip. This layer has a CTE value that matches the glass substrate, allowing it to expand and contract with the substrate during thermal processes while preventing the semiconductor chip from offsetting. The layer acts as a mediator that absorbs the thermal expansion mismatch between the glass substrate and the encapsulant, thereby maintaining chip position accuracy while enabling proper encapsulant formation.
Solution Approach 2:
The invention changes the CTE parameter of the offset suppression layer to match the glass substrate (both having CTE values of approximately 0.3 ppm/K). This parameter matching ensures that both layers expand and contract at the same rate during thermal processing, preventing relative displacement between the glass substrate and the semiconductor chip, thus resolving the position accuracy issue while maintaining reliable encapsulant formation.
2Ease of manufacture
If the CTE of the glass substrate is much less than the CTE of the encapsulant, then the encapsulant can be properly formed, but the outward expansion amount and inward shrinkage amount of the semiconductor chip are not the same, causing the chip to offset and not return to its original position
Solution Approach 1:
The offset suppression layer serves as a mediator that decouples the CTE mismatch between the glass substrate and the encapsulant. By placing this layer between the substrate and the chip, it allows the encapsulant to be properly molded while the suppression layer absorbs the differential thermal expansion, keeping the chip stable and preventing offset during both heating and cooling cycles.
Solution Approach 2:
The invention introduces a new parameter relationship: the offset suppression layer has a CTE value (0.3 ppm/K) that matches the glass substrate, creating a CTE-matched pair. This parameter change ensures that during thermal cycling, both the substrate and suppression layer expand and contract together, maintaining the chip's position stability while still allowing the encapsulant to be properly formed with its higher CTE value.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The offset suppression layer effectively prevents the offset of electronic elements by ensuring that the outward expansion and inward shrinkage amounts are equal or close, thereby maintaining the original position of the semiconductor chips and reducing yield loss.
Implementation Method 1
the coefficient of thermal expansion (CTE) of the glass substrate is much less than the coefficient of thermal expansion of the encapsulant... the glass substrate will expand outward when the encapsulant is heated and shrink inward when the encapsulant is cooled
Implementation Method 2
the glass substrate will expand outward when the encapsulant is heated and shrink inward when the encapsulant is cooled
Data Source
AI summary
An electronic package and a manufacturing method thereof are provided, in which an offset suppression layer is formed on a carrier, a first electronic element and a second electronic element are respectively disposed on the offset suppression layer, and an encapsulant is formed on the offset suppression layer to respectively cover the first electronic element and the second electronic element. The offset suppression layer effectively suppresses or prevents possible offset caused by the encapsulant to the first electronic element and the second electronic element, thereby avoiding yield loss of the semiconductor package.