Package-on-Package Structure with Backside Connection for Thermal Stress Reduction
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Solution Overview
Problem
Current three-dimensional stacking technologies for semiconductor packaging face challenges in achieving higher packaging densities while maintaining smaller package sizes and reducing thermal stress and manufacturing costs.
Innovation Solution
The method involves forming a package-on-package (PoP) structure using a backside connection structure with conductive pins and a redistribution layer, where a first semiconductor die is encapsulated with an insulating material, and a second package is stacked and electrically connected through conductive balls, allowing for smaller package sizes and reduced thermal stress, and incorporating a de-bonding layer for carrier separation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If traditional semiconductor packaging methods are used, then manufacturing processes are simpler, but packaging density is lower and package sizes are larger
Solution Approach 1:
The patent implements package-on-package (PoP) stacking technology that transitions from two-dimensional planar packaging to three-dimensional vertical stacking. Multiple semiconductor packages are stacked vertically and connected through conductive pins penetrating through the package structure, enabling higher packaging density by utilizing the vertical dimension while maintaining compact footprint.
Solution Approach 2:
The patent employs a nested structure where one package is positioned within or alongside another package in the PoP configuration. The inner package contains semiconductor components and is surrounded by the outer package structure, allowing multiple functional units to be integrated in a compact arrangement that maximizes space utilization.
2Quantity of substance
If feature sizes are reduced to increase integration density, then more components can be integrated, but manufacturing precision requirements increase
Solution Approach 1:
The patent divides the semiconductor system into multiple separate packages that are stacked and interconnected. Each package can be manufactured independently with standard feature sizes, avoiding the need to reduce minimum feature sizes across the entire system. The segmentation allows each package to be optimized separately while achieving high overall integration density through vertical stacking.
3Ease of manufacture
If larger packages are used to accommodate more components, then manufacturing is easier, but package size increases and thermal stress increases
Solution Approach 1:
Instead of increasing package footprint area to accommodate more components, the patent stacks multiple packages vertically in the third dimension. This approach maintains small individual package sizes with standard manufacturing processes while achieving high component capacity through multi-layer integration, effectively trading horizontal expansion for vertical growth.
4Object-affected harmful factors
If conventional packaging structures are used, then thermal stress is higher, but structure simplicity is maintained
Solution Approach 1:
The patent introduces intermediary structures including conductive pins that penetrate through packages, underfill materials in gaps between packages, and redistribution layers for electrical connections. These intermediary elements serve multiple functions: mechanical support to distribute thermal stress, electrical interconnection between stacked packages, and structural alignment, thereby reducing thermal stress while managing the increased structural complexity through multifunctional components.
Data Source
AI summary
A package-on-package structure including a first and second package is provided. The first package includes a first semiconductor die, a plurality of conductive pins, an insulating encapsulant, a backside connection structure and a redistribution layer. The conductive pins are surrounding the first semiconductor die and have a base portion with a first width and a body portion with a second width, the base portion is connected to the body portion and the first width being larger than the second width. The insulating encapsulant is encapsulating the first semiconductor die and the conductive pins. The backside connection structure is disposed on the first semiconductor die and electrically connected to the conductive pins. The redistribution layer is disposed on the first semiconductor die, and electrically connected to the first semiconductor die and the conductive pins. The second package is stacked on the first package and electrically connected to the backside connection structure.