Package-on-Package IC Packaging with Buffer Layer Encapsulation
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Solution Overview
Problem
Current package-on-package (PoP) integrated circuit packaging systems face limitations in miniaturization, cost, and input/output connectivity, hindering the integration of complex die and package configurations and increasing costs.
Innovation Solution
The implementation of an encapsulation system with a mold chase and a buffer layer attached, which allows for the formation of a base integrated circuit package with a partially exposed interconnect, enabling easier mold design, cost-effective tooling, and improved coplanarity, while facilitating easier release and disengagement, and supporting increased connectivity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If package-on-package stacking is implemented to increase IC density, then packaging density improves, but device complexity and manufacturing difficulty increase
Solution Approach 1:
The patent divides the package structure into separate modular units (first package and second package) that can be independently manufactured and then stacked. Each package contains its own substrate, component, and encapsulation, allowing independent optimization and simplifying the overall manufacturing process while achieving high density through vertical integration.
Solution Approach 2:
The patent transitions from planar packaging to three-dimensional package-on-package stacking, moving components from a two-dimensional substrate surface to a vertical stack configuration. This dimensional change dramatically increases IC density by utilizing the vertical space above the substrate rather than expanding the substrate area.
2Adaptability or versatility
If more I/O connections are added to accommodate increasing functionality, then device capability improves, but package size and complexity increase
Solution Approach 1:
The patent provides I/O connections through the vertical stacking dimension rather than expanding the horizontal substrate area. Multiple I/O connections are achieved by stacking additional packages vertically, each contributing their own I/O capabilities, thereby increasing connectivity without proportionally increasing package footprint or structural complexity.
3Volume of moving object
If miniaturization is pursued to reduce device size, then portability improves, but manufacturing precision requirements increase
Solution Approach 1:
The patent segments the miniaturized package into modular stacked units, each with standardized interfaces. This segmentation allows each module to be manufactured with controlled precision using existing processes, then assembled through alignment features that accommodate normal manufacturing tolerances, thereby achieving miniaturization without requiring extreme precision throughout the entire manufacturing chain.
Solution Approach 2:
The patent incorporates alignment features and positioning structures during the individual package manufacturing stage, preparing the components for precise stacking before assembly. This preliminary action ensures that when packages are stacked, the alignment is already partially established through built-in mechanical features, reducing the precision requirements for the final assembly process.
4Ease of manufacture
If buffer layer is used during encapsulation to protect interconnect, then manufacturing ease improves, but interconnect exposure control becomes critical
Solution Approach 1:
The patent applies a buffer layer during encapsulation that extends beyond the minimum required coverage area. This excessive buffering provides a margin of error that accommodates normal variations in interconnect position and encapsulation depth, ensuring that interconnects remain protected while allowing for easier manufacturing without requiring precise control of the buffer layer boundaries.
Data Source
AI summary
A method of manufacture of an integrated circuit packaging system includes: providing an encapsulation system having a mold chase with a buffer layer attached thereto; forming a base integrated circuit package including: providing a base substrate, connecting an exposed interconnect to the base substrate, a portion of the exposed interconnect having the buffer layer attached thereon, mounting a base component over the base substrate, and forming a base encapsulation over the base substrate and the exposed interconnect using the encapsulation system; and releasing the encapsulation system providing the portion of the exposed interconnect exposed from the base encapsulation, the exposed interconnect having characteristics of the buffer layer removed.