Package-on-Package Semiconductor Stacking for Direct Mainboard Mounting
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Solution Overview
Problem
The existing package-on-package (PoP) technologies face challenges in efficiently integrating multiple units of an application processor chip due to spatial limitations and the need for direct mounting on mainboards, which is hindered by the redistribution of I/O terminals in fan-in semiconductor packages and the complexity of fan-out packages.
Innovation Solution
A PoP system is proposed where a first semiconductor package with more units is electrically connected to a second semiconductor package, each containing specific units of an application processor chip, allowing for enhanced functionality and compact design by separating core units and redistributing I/O terminals, enabling direct mounting on printed circuit boards without additional substrates.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If fan-in semiconductor packages are used to redistribute I/O terminals, then I/O terminal redistribution is achieved, but direct mounting on mainboards is hindered
Solution Approach 1:
The application processor chip is divided into multiple semiconductor chips, each containing specific units. This segmentation allows the PoP structure to mount directly on mainboards without requiring complex fan-in package redistribution layers, as each chip maintains its own I/O terminal configuration suitable for direct mounting.
Solution Approach 2:
The patent transitions from a planar fan-in package structure to a three-dimensional PoP structure. By stacking semiconductor chips vertically and establishing electrical connections through the stack, the system achieves direct mounting capability while maintaining I/O terminal functionality without requiring additional substrate redistribution layers.
2Area of stationary object
If multiple units of application processor chip are integrated in a single chip, then functionality is consolidated, but spatial limitations are encountered
Solution Approach 1:
Multiple semiconductor chips are nested vertically in a PoP configuration, with chips stacked one on top of another. This nesting approach consolidates multiple functional units into a compact three-dimensional structure, reducing the planar area occupation while maintaining high functional integration through vertical stacking and inter-chip electrical connections.
3Adaptability or versatility
If fan-out packages are used for I/O terminal redistribution, then I/O terminal flexibility is improved, but package complexity increases
Solution Approach 1:
The patent segments the application processor functionality across multiple semiconductor chips, each with optimized I/O terminal configurations. This segmentation eliminates the need for complex fan-out package structures that would otherwise be required to achieve similar I/O flexibility, as each chip can be directly mounted with its native I/O arrangement.
Data Source
AI summary
A package-on-package includes a first semiconductor package including a first semiconductor chip and a second semiconductor package, disposed on the first semiconductor package, including a second semiconductor chip electrically connected to the first semiconductor chip. Each of the first and second semiconductor chips includes one or more units. The number of units of the first semiconductor chip is greater than the number of units of the second semiconductor chip. The one or more units of the first semiconductor chip and the one or more units of the second semiconductor chip implement a function of an application processor chip.