Package-on-Package IC Packaging with Base Exposed Interconnect
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Solution Overview
Problem
Current integrated circuit packaging technologies face challenges in achieving smaller size, lower cost, and increased functionality while maintaining performance, as they are limited by the space available for mounting individual die on a substrate, leading to compact but costly and inefficient designs.
Innovation Solution
The method involves a base substrate with a component and interconnects, a stack device mounted over the component, and a base exposed interconnect that is partially exposed from the encapsulation, allowing direct electrical connection between the component and the stack device without passing through additional wires or substrate traces, thereby reducing package size and simplifying routing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If conventional packaging methods are used with mature manufacturing processes, then manufacturing cost is reduced, but package dimensions cannot be reduced
Solution Approach 1:
The patent transitions from traditional planar substrate mounting to a three-dimensional stacked architecture where components are arranged vertically in multiple layers. This dimensional change allows multiple components to occupy the same footprint area, reducing the overall package dimensions while maintaining compatibility with conventional manufacturing processes that can form vertical interconnects and stacked structures.
Solution Approach 2:
The patent implements a nested structure where smaller components and interconnect elements are positioned within and between larger structural elements. The stacked configuration allows lower-layer components to be nested beneath upper-layer components, maximizing space utilization and reducing the horizontal footprint of the package while keeping manufacturing costs low through process reuse.
2Quantity of substance
If more integrated circuits are packed into smaller physical space, then packaging density increases, but manufacturing complexity increases
Solution Approach 1:
The patent divides the packaging system into discrete modular layers, each containing specific components and interconnect structures. This segmentation allows each layer to be manufactured and prepared independently using conventional processes, then assembled into a stacked configuration. The modular approach increases packaging density by utilizing vertical space while managing manufacturing complexity through standardized, repeatable layer fabrication.
Solution Approach 2:
The patent employs universal manufacturing processes that can create multiple functions within the same structural elements. For example, the substrate and interconnect layers serve both as mechanical support structures and as electrical connection pathways. This multi-functionality allows higher packaging density to be achieved without proportionally increasing manufacturing complexity, as the same processes fabricate both structural and functional elements.
3Reliability
If signal traces pass through substrate and additional wires, then electrical connection is established, but signal trace length increases
Solution Approach 1:
The patent uses vertical interconnects that travel through the stacked layers rather than horizontal traces across the substrate plane. This vertical routing in the z-dimension significantly shortens the signal path length compared to traditional planar routing, while maintaining reliable electrical connections through direct vias and contact structures between stacked components.
Solution Approach 2:
The patent extracts the signal transmission function from the substrate plane by implementing dedicated vertical interconnect structures that directly bridge components across layers. This separation of concerns allows the substrate to focus on mechanical support while the extracted interconnect structures provide optimized, short-length electrical pathways, improving signal integrity and reducing trace length.
Data Source
AI summary
A method of manufacture of an integrated circuit packaging system includes: providing a base substrate; attaching a component over the base substrate; attaching a component interconnect to the base substrate and a perimeter of the component; mounting a stack device over the component; attaching a base exposed interconnect directly on the component and next to the component interconnect; and forming a base encapsulation over the base substrate, the component, and the component interconnect, the base exposed interconnect partially exposed from the base encapsulation.