Package-on-Package IC Packaging with Interposer Window
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Solution Overview
Problem
Conventional integrated circuit packaging technologies face challenges in achieving smaller, thinner, and higher-density packages with low manufacturing costs, particularly in portable electronic devices, where traditional single chip packaging fails to meet the requirements for slim, compact, and multi-functional designs.
Innovation Solution
The proposed integrated circuit packaging system involves a base substrate with a mounted base integrated circuit, peripheral and central interconnects, and an interposer with a window, allowing for direct connections between the base integrated circuit and the interposer, which reduces signal routing complexity and enhances high-speed performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If traditional single chip packaging is used, then manufacturing process is simple, but packaging size and thickness cannot be reduced
Solution Approach 1:
The patent implements package-on-package (POP) structure where a first chip package is mounted on a substrate and a second chip package is mounted on top of the first chip package, creating a nested vertical stacking configuration. This nesting approach reduces the horizontal footprint and overall packaging size while maintaining multiple functional chips within a compact volume.
Solution Approach 2:
The patent transitions from traditional horizontal single-chip packaging to vertical three-dimensional stacking by mounting the second chip package on top of the first chip package. This dimensional change from 2D to 3D packaging enables significant reduction in packaging area and thickness while accommodating multiple chips.
2Volume of moving object
If two chip packages are stacked by conventional POP technique, then packaging size is reduced, but electrical connection complexity increases due to solder requirements
Solution Approach 1:
The patent introduces a substrate as an intermediary element between the first chip package and the second chip package. The substrate provides mounting surfaces and electrical interconnection pathways, mediating the electrical connections between chips without requiring direct solder joints between the stacked packages, thereby simplifying the manufacturing process.
Solution Approach 2:
The patent divides the electrical connection function into separate segments: the substrate handles electrical interconnections between chips through its circuit traces, while the chip packages focus on their individual functions. This segmentation of connection responsibilities simplifies the overall manufacturing by eliminating complex direct soldering requirements between stacked packages.
3Length of stationary object
If chip packages are made smaller and thinner for portable devices, then portability is improved, but signal routing complexity and manufacturing difficulty increase
Solution Approach 1:
The patent adopts vertical stacking architecture where signal routing is organized in layers through the substrate and between stacked packages. This three-dimensional signal routing approach reduces the horizontal routing complexity that would otherwise be required in planar configurations, enabling thinner packages with manageable signal paths.
Solution Approach 2:
The substrate serves as an intermediary that manages signal routing between the first and second chip packages. By providing controlled impedance traces and routing layers within the substrate, the complex signal paths are organized and managed systematically, reducing overall routing complexity despite the vertical stacking configuration.
Data Source
AI summary
A method of manufacture of an integrated circuit packaging system includes: providing a base substrate having a base substrate top side; mounting a base integrated circuit over the base substrate top side, the base integrated circuit having an active side opposite an inactive side with the inactive side facing the base substrate top side; attaching a peripheral interconnect to the base substrate top side and a device peripheral pad of the base integrated circuit at the active side; mounting an interposer over the base integrated circuit and the peripheral interconnect, the interposer having an interposer top side and a window; and attaching a central interconnect to the interposer top side and a device central pad of the base integrated circuit at the active side, the central interconnect through the window.