Package-on-Package IC Stacking with Recessed Encapsulation

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Solution Overview

Problem

Current integrated circuit packaging systems face challenges in achieving thinner, less expensive, and more reliable package-on-package (PoP) configurations with increasing miniaturization demands, particularly in portable devices, where existing solutions have not adequately addressed the need for higher performance, lower costs, and greater packaging density.

Innovation Solution

The method involves a base substrate with a first and second base integrated circuit stacked on top of each other, attached via a stacking interconnect, and encapsulated with a base encapsulation featuring a recess and step portion, allowing for a reduced profile and improved reliability by exposing the stacking interconnect and eliminating delamination risks.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If package-on-package configuration is used to increase packaging density, then packaging density is improved, but profile thickness increases

Engineering Contradiction:
Improvepackaging densityVSAvoidprofile thickness
Core Design Contradiction:
Quantity of substanceVSLength of moving object

Solution Approach 1:

The patent transitions from horizontal packaging arrangement to vertical stacking configuration, utilizing the third dimension (height/vertical space) to increase packaging density. Multiple integrated circuits are stacked vertically on the base substrate, allowing greater component density without increasing the horizontal footprint, thereby resolving the contradiction between packaging density and profile thickness.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The patent implements nested packaging by placing integrated circuits within encapsulation structures that are themselves mounted on the base substrate. The first and second integrated circuits are nested within the base encapsulation, which provides structural support and protection while enabling vertical stacking. This nesting approach allows multiple components to occupy overlapping spatial volumes, increasing packaging density without proportionally increasing overall profile thickness.

Inventive Principle:
Principle #7Nested doll (Nesting)

2Quantity of substance

If multiple integrated circuits are stacked vertically to increase density, then packaging density is improved, but manufacturing complexity increases

Engineering Contradiction:
Improvepackaging densityVSAvoidmanufacturing complexity
Core Design Contradiction:
Quantity of substanceVSDevice complexity

Solution Approach 1:

The patent divides the packaging system into distinct modular segments: base substrate, first integrated circuit, second integrated circuit, base encapsulation, and interconnect structures. Each segment can be manufactured and prepared independently, then assembled through standardized processes. This segmentation reduces manufacturing complexity by breaking down the complex task of vertical stacking into manageable, repeatable steps, while still achieving high packaging density.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent employs preliminary actions by pre-attaching integrated circuits to the base substrate and pre-forming the base encapsulation structure before final assembly. The stacking interconnects are prepared in advance on the base substrate, and circuits are pre-positioned and secured. These preliminary steps simplify the overall manufacturing process by reducing the complexity of final assembly operations, enabling efficient vertical stacking while maintaining high packaging density.

Inventive Principle:
Principle #10Preliminary action

3Reliability

If encapsulation is formed to protect integrated circuits, then reliability is improved, but access to stacking interconnect becomes difficult

Engineering Contradiction:
Improveprotection reliabilityVSAvoidinterconnect accessibility
Core Design Contradiction:
ReliabilityVSEase of operation

Solution Approach 1:

The base encapsulation structure implements local quality by providing differential coverage: it encapsulates and protects the integrated circuits and interconnect structures in certain regions, while deliberately leaving exposed portions in other regions. Specifically, the encapsulation covers the circuits for protection but exposes the stacking interconnects to enable electrical connection. This localized differentiation resolves the contradiction by providing protection where needed while maintaining accessibility where required.

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The patent extracts the stacking interconnect structures from within the encapsulation volume by forming the encapsulation to expose these interconnects. Rather than fully enclosing all components, the encapsulation is designed to leave the stacking interconnects accessible from the exterior. This extraction approach allows the encapsulation to provide protection for vulnerable components while maintaining easy access to the interconnects for electrical connection, resolving the contradiction between protection and accessibility.

Inventive Principle:
Principle #2Taking out (Extraction)

Data Source

PatentUS7968995B2Integrated circuit packaging system with package-on-package and method of manufacture thereof
Publication Date: 2011.06.28 STATS CHIPPAC MANAGEMENT PTE LTD
  • US7968995B2 patent drawing
  • US7968995B2 patent drawing
  • US7968995B2 patent drawing

AI summary

A method of manufacture an integrated circuit packaging system includes: providing a base substrate; mounting a first base integrated circuit over the base substrate; mounting a second base integrated circuit over the first base integrated circuit; attaching a stacking interconnect to the base substrate and adjacent to the first base integrated circuit; and forming a base encapsulation, having a recess portion from a corner of the base encapsulation and a step portion adjacent to the recess portion, with the step portion over the second base integrated circuit and the recess portion exposing the stacking interconnect.