Package-on-Package Device Layout for Signal Routing Efficiency
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Solution Overview
Problem
Existing package-on-package (PoP) devices face challenges in achieving high-speed and compactness while maintaining signal quality and power delivery due to increased size and complex signal interconnection routing.
Innovation Solution
A novel PoP device layout where solder balls are placed only on specific side surfaces of the package substrate, reducing the device's width and simplifying signal interconnection routing, and a method of fabricating this device that includes a mold layer and under-fill resin to prevent internal voids and enhance performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a plurality of semiconductor chips or integrated circuits are provided in each package to meet increasing demand for high-performance electronic systems, then the device performance is improved, but the size of the PoP device increases
Solution Approach 1:
The patent transitions from a planar arrangement of semiconductor chips to a three-dimensional stacked configuration. Multiple packages are vertically stacked with solder balls connecting package substrates across different layers, enabling high-density integration without increasing the lateral footprint of the device.
Solution Approach 2:
The patent implements a nested structure where multiple semiconductor packages are stacked one on top of another. Each package contains chips or ICs, and the packages themselves are nested in a vertical arrangement, with solder balls providing interconnections between nested package layers, achieving compact high-performance integration.
2Area of stationary object
If multiple packages are stacked to create PoP device, then compactness is achieved, but signal interconnection routing becomes more complex
Solution Approach 1:
The patent segments the interconnection structure into discrete solder balls positioned at specific locations on package substrates. Each solder ball serves as an independent connection point, and the segmentation of connection regions allows for simplified routing design compared to traditional complex interconnect schemes.
Solution Approach 2:
The patent extracts and eliminates unnecessary solder balls from certain regions of the package substrate. By selectively removing solder balls from areas not requiring interconnections, the design simplifies the overall routing complexity while maintaining essential signal pathways between stacked packages.
3Speed
If interconnection lines are lengthened to connect stacked packages, then package stacking is achieved, but signal quality deteriorates
Solution Approach 1:
The patent uses vertical stacking in the third dimension to reduce lateral interconnection distances. Solder balls provide direct vertical connections between package substrates, significantly shortening signal path lengths compared to lateral routing in planar configurations, thereby improving signal quality and speed.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution results in a more compact PoP device with improved signal-routing efficiency and performance by reducing the device's width, simplifying interconnection routing, and preventing signal interference, thereby enhancing signal quality and power delivery.
Implementation Method 1
a plurality of solder balls provided between the first and second package substrates to connect the first and second package substrates with each other
Implementation Method 2
a method of fabricating a package-on-package (PoP) device, in which a mold layer can be formed without producing undesirable internal voids
Data Source
AI summary
Provided are a package-on-package device and a method of fabricating the same. In the device, solder balls may be disposed on two opposing side regions of a package substrate, such that the device can have a reduced size or width. In addition, input/output pads of the logic chip and the solder balls, which need to be directly connected to each other, can be disposed adjacent to each other. As a result, it is possible to improve routability of signals to and from the solder balls and to reduce the lengths of the interconnection lines. Accordingly, it is possible to reduce any signal interference, to increase signal delivery speed, and to improve signal-quality and power-delivery properties.