Package-on-Package Semiconductor Stacking for High Density
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Solution Overview
Problem
The semiconductor industry faces challenges in achieving smaller form factors, cost-effectiveness, increased performance, and lower power consumption as demand grows for miniaturization, higher speed, and greater bandwidth, which existing packaging techniques struggle to meet, especially at sub-20 nm nodes.
Innovation Solution
The development of package-on-package semiconductor devices, where active circuits are fabricated on different wafers and packages stacked with a standard interface to route signals, allowing for higher density, smaller form factors, cost-effectiveness, and reduced power consumption through techniques like redistribution layers, underfill materials, and thinning processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If traditional packaging techniques are used, then manufacturing simplicity is maintained, but integration density and form factor reduction are insufficient
Solution Approach 1:
The patent transitions from planar packaging to three-dimensional stacked packaging, arranging multiple semiconductor devices in vertical layers rather than side-by-side on a single substrate. This dimensional change enables higher integration density by utilizing the Z-axis space, allowing multiple devices to occupy a smaller footprint area while maintaining electrical connectivity through vertical interconnect structures.
Solution Approach 2:
The patent implements a nested structure where smaller semiconductor devices are placed within and around larger devices, similar to nested dolls. Multiple devices are stacked and interconnected in a hierarchical arrangement, with each layer containing functional devices that are electrically connected to layers above and below, maximizing space utilization and integration density.
2Volume of moving object
If device size is reduced for miniaturization, then form factor is improved, but signal routing and electrical connectivity become more difficult
Solution Approach 1:
The patent routes signals between stacked devices through vertical interconnect structures that extend through the thickness of intermediate substrates, utilizing the third dimension for signal transmission. This vertical routing approach eliminates the need for complex lateral signal paths, enabling efficient electrical connectivity between miniaturized devices in different layers while maintaining compact form factor.
3Manufacturing precision
If multiple devices are stacked to increase density, then integration density is improved, but stress and reliability challenges increase
Solution Approach 1:
The patent introduces intermediate substrates as mediator layers between stacked semiconductor devices. These substrates provide mechanical support, thermal management, and electrical interconnection functions, distributing and managing stresses generated by thermal expansion mismatches and mechanical loads. The intermediary substrates act as stress-absorbing elements that protect the fragile semiconductor devices while enabling reliable vertical stacking.
Data Source
AI summary
A method comprises attaching a semiconductor die on a first side of a wafer, attaching a first top package on the first side of the wafer and attaching a second top package on the first side of the wafer. The method further comprises depositing an encapsulation layer over the first side of the wafer, wherein the first top package and the second top package are embedded in the encapsulation layer, applying a thinning process to a second side of the wafer, sawing the wafer into a plurality of chip packages and attaching the chip package to a substrate.