Package-on-Package Stacking for Signal Speed and Area
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Solution Overview
Problem
The semiconductor industry faces challenges in reducing the size of electronic components and packaging to accommodate increased integration density, requiring smaller packages that utilize less area while maintaining efficient electrical connections and signal speed.
Innovation Solution
The method involves forming package-on-package structures through a series of redistribution layers and encapsulation steps, including the use of carrier substrates, release layers, dielectric and metallization patterns, and external electrical connectors to create a compact and efficient electrical interconnect system, allowing for shorter electrical connections and increased signal speed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If package size is reduced to accommodate increased integration density, then area utilization is improved, but electrical connection efficiency and signal speed may deteriorate
Solution Approach 1:
The patent transitions from planar packaging to three-dimensional package-on-package stacking, where multiple packages are vertically integrated through redistribution layers and encapsulation. This vertical dimension allows shorter electrical connections between dies while maintaining compact footprint, thereby preserving signal speed despite reduced package area.
Solution Approach 2:
The patent implements nested packaging where a first package containing a first die is embedded within a second package structure. The first package is encapsulated and integrated into the second package's redistribution layers, creating a compact nested configuration that reduces overall area while maintaining efficient electrical pathways.
2Area of stationary object
If package size is reduced, then area utilization is improved, but electrical connection length may increase causing higher resistance
Solution Approach 1:
By stacking packages vertically in the third dimension, the patent shortens the physical distance between electrical connections between dies. This vertical integration reduces connection length and resistance, improving electrical reliability while maintaining small footprint area.
Solution Approach 2:
The patent introduces redistribution layers as intermediary structures that facilitate efficient electrical connections between stacked packages. These redistribution layers act as mediators that route signals through optimized pathways, reducing connection resistance and improving electrical reliability in the compact package-on-package structure.
3Productivity
If more components are integrated into a given area, then integration density is improved, but manufacturing complexity increases
Solution Approach 1:
The patent divides the integrated circuit system into separate stackable packages, each containing individual dies. This segmentation allows independent fabrication and testing of each package, then combines them through standardized redistribution layers, thereby achieving high integration density while managing manufacturing complexity through modular assembly.
Solution Approach 2:
The patent creates universal package structures with standardized redistribution layers and encapsulation that can accommodate multiple different dies and configurations. This multi-functional platform enables high integration density through flexible component arrangement while simplifying manufacturing through standardized processes and interchangeable components.
Data Source
AI summary
Methods of forming and structures of packages are discussed herein. In an embodiment, a method includes forming a back side redistribution structure, and after forming the back side redistribution structure, adhering a first integrated circuit die to the back side redistribution structure. The method further includes encapsulating the first integrated circuit die on the back side redistribution structure with an encapsulant, forming a front side redistribution structure on the encapsulant, and electrically coupling a second integrated circuit die to the first integrated circuit die. The second integrated circuit die is electrically coupled to the first integrated circuit die through first external electrical connectors mechanically attached to the front side redistribution structure.