Package-on-Package Stacking With Through Silicon Via Interposer
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Solution Overview
Problem
Current integrated circuit packaging systems face challenges with high failure rates due to solder joint cracks and delamination under temperature and humidity changes, limited integrated circuit density, and difficulties in testing individual integrated circuits in multi-chip packages, which complicates manufacturing and increases costs.
Innovation Solution
The implementation of a package-on-package stacking system using a through silicon via interposer, where a top package with a stacked integrated circuit die is coupled to a base package with a substrate via stacked interconnects, allowing for independent testing and reduced thickness, thereby improving yield and reducing fragility.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If vertically stacked chips are assembled on plastic or ceramic interposers using solder balls, then integrated circuit density increases, but failure rates increase due to solder joint cracks and delamination under temperature and humidity changes
Solution Approach 1:
The patent introduces a substrate as an intermediary component between the integrated circuits and the external environment. This substrate provides a stable mounting platform that reduces stress on solder joints and prevents delamination, thereby maintaining high integrated circuit density while improving reliability under temperature and humidity variations.
Solution Approach 2:
The patent employs composite material structures in the packaging system, combining different materials with complementary properties. The substrate integrates materials that provide both mechanical support and thermal stability, reducing the harmful effects of thermal expansion mismatches and preventing solder joint cracks while maintaining high circuit density.
2Area of stationary object
If multiple integrated circuits are mounted on a single substrate to increase density, then board area is reduced, but manufacturing complexity increases and individual circuit testing becomes difficult
Solution Approach 1:
The patent divides the packaging system into modular units, with each integrated circuit having its own designated mounting location and interconnection path on the substrate. This segmentation allows for standardized manufacturing processes and enables individual testing of each circuit module before final assembly, reducing overall manufacturing complexity despite high density.
Solution Approach 2:
The patent implements preliminary testing and validation of individual integrated circuits and their interconnections on the substrate before final package assembly. This preliminary action identifies manufacturing defects early, simplifies rework processes, and ensures each circuit functions correctly in the high-density configuration, thereby reducing overall manufacturing complexity.
3Quantity of substance
If conventional multi-chip packages are pre-assembled before testing, then integrated circuit density increases, but assembly process yield decreases due to inability to identify known-good-die
Solution Approach 1:
The patent performs preliminary testing of individual integrated circuits and their interconnections on the substrate before final package assembly. This allows identification of known-good-die and defective components, enabling selective assembly of only functional units, thereby maintaining high integrated circuit density while improving assembly process yield.
Solution Approach 2:
The patent incorporates feedback mechanisms during the assembly process, where test results from preliminary circuit validation are used to guide subsequent assembly decisions. This feedback loop ensures that only verified functional circuits are assembled into the final high-density package, improving both yield and reliability.
Data Source
AI summary
A method of manufacture of an integrated circuit packaging system including: forming a top package including: providing a through silicon via interposer having a through silicon via; coupling a stacked integrated circuit die to the through silicon via, and testing a top package; forming a base package including: providing a substrate, coupling a base integrated circuit die to the substrate, and testing a base package; and coupling a stacked interconnect between the top package and the base package.