Package-On-Package Structure for Thin IC Stacking
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Solution Overview
Problem
Conventional integrated circuit packaging methods result in thick and large packages due to the need for small pitch electrical connections, which complicates the formation of micro-bumps and increases the complexity of component integration.
Innovation Solution
A Package-On-Package (POP) structure is formed by embedding device dies in a molding material with Through Assembly Vias (TAVs) and Redistribution Lines (RDLs), allowing for a thinner and more compact design by stacking device dies and passive components rather than bonding them to a common interposer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional bonding methods with interposers are used to integrate multiple components, then electrical connectivity between components is achieved, but the package thickness and area increase significantly
Solution Approach 1:
The patent transitions from a planar integration architecture to a three-dimensional stacked architecture. Multiple device dies are vertically stacked and bonded to each other through wafer-level bonding, eliminating the need for a large-area interposer. This dimensional change allows electrical connections to be made through vertical vias and bump structures rather than requiring extensive lateral routing on a flat substrate, thereby reducing both package thickness and area while maintaining connectivity.
Solution Approach 2:
The patent extracts and eliminates the interposer component from the conventional packaging architecture. By directly bonding device dies to each other in a stacked configuration, the interposer is removed entirely, reducing the overall package thickness and simplifying the interconnection structure. The electrical connectivity function previously performed by the interposer is now achieved through direct die-to-die bonding with integrated via structures.
2Adaptability or versatility
If small pitch electrical connections are used to connect components to the interposer, then component integration is achieved, but the formation of micro-bumps becomes technically challenging
Solution Approach 1:
The patent performs preliminary actions during the wafer-level bonding process by pre-forming via structures and conducting electrical interconnections before the actual device stacking. The through-silicon vias (TSVs) and other interconnect structures are created in advance during wafer fabrication, allowing for more relaxed pitch requirements compared to post-bonding micro-bump formation. This preliminary integration of electrical connections simplifies the subsequent stacking process and reduces manufacturing complexity.
Solution Approach 2:
The patent segments the interconnection function into multiple distinct structural elements: through-silicon vias for vertical connections, bump structures for inter-die bonding, and redistribution layers for signal routing. This segmentation allows each element to be optimized independently for its specific function, reducing the overall complexity of achieving small-pitch connections compared to forming all connections as micro-bumps on an interposer.
3Adaptability or versatility
If multiple components are bonded to a common interposer, then functional integration is achieved, but the package area becomes large
Solution Approach 1:
The patent achieves functional integration of multiple components by stacking device dies vertically in the third dimension rather than arranging them laterally on a flat interposer. This dimensional transition concentrates the integrated functionality into a compact footprint, reducing package area while maintaining all required functional connections through vertical interconnect structures.
Solution Approach 2:
The patent merges multiple device dies into a single stacked assembly where the functional elements of different components are integrated in close proximity. By bonding multiple dies together with their respective active surfaces facing each other, the patent combines the functionality of separate components into one compact unit, eliminating the need for a large-area interposer to host all components and their interconnections.
Data Source
AI summary
A device includes a top package bonded to a bottom package. The bottom package includes a molding material, a device die molded in the molding material, a Through Assembly Via (TAV) penetrating through the molding material, and a redistribution line over the device die. The top package includes a discrete passive device packaged therein. The discrete passive device is electrically coupled to the redistribution line.