Package-on-Package System with Through Vias
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Solution Overview
Problem
Existing Package-in-Package (PiP) and Package-on-Package (PoP) systems lack versatility and reliability, are prone to warping during fabrication, and have high costs, making them unsuitable for integration into larger multi-chip modules.
Innovation Solution
A package-on-package system is developed with a substrate connection and semiconductor die attached using an adhesive, surrounded by an encapsulant with through vias created by applying solder, which reduces warping and costs while enhancing interconnection capabilities.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If standard PiP or PoP packages are used, then package functionality is achieved, but warping occurs during fabrication and reliability is insufficient
Solution Approach 1:
The patent segments the package structure into multiple functional layers: substrate connection layer, adhesive layer, semiconductor die layer, encapsulant layer, and through-via layer. This segmentation allows each layer to be optimized independently for its specific function, reducing overall warping while maintaining reliability
Solution Approach 2:
The patent employs composite material structures combining different materials with complementary properties: adhesive materials for bonding, encapsulant materials for protection and planarization, and solder materials for through-vias. This composite approach balances thermal expansion coefficients and mechanical properties to reduce warping
2Adaptability or versatility
If existing PiP or PoP systems are implemented, then multi-chip integration is achieved, but cost is high and versatility is insufficient
Solution Approach 1:
The patent creates a universal package module design with standardized substrate connections and through-vias that can be integrated into various multi-chip module configurations. The modular encapsulant structure with coplanar surfaces enables the same basic design to serve multiple integration purposes, increasing versatility while reducing development costs
Solution Approach 2:
The patent performs preliminary testing and characterization of the package module before final integration into the multi-chip system. The coplanar encapsulant surfaces and pre-formed through-vias allow for pre-assembly verification, reducing costly rework and improving manufacturing efficiency
3Adaptability or versatility
If through vias are created by applying solder into through openings, then interconnection capabilities are increased, but manufacturing complexity increases
Solution Approach 1:
The patent transitions from planar interconnections to three-dimensional through-vias that penetrate the encapsulant vertically. This dimensional change enables multiple interconnection paths through the package thickness, significantly increasing interconnection capabilities while the standardized via formation process keeps manufacturing complexity manageable
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The system reduces warping and costs, improving reliability and enabling easier integration into larger multi-chip modules by providing a low-cost, modular package with increased interconnection capabilities.
Implementation Method 1
attaching a semiconductor die to the substrate connection using an adhesive
Implementation Method 2
creating through vias by applying solder into the through openings
Data Source
AI summary
A method of manufacture of a package-on-package system includes: providing a substrate connection; attaching a semiconductor die to the substrate connection using an adhesive, with the substrate connection affixed directly by the adhesive; forming an encapsulant around the semiconductor die to have a bottom exposed surface coplanar with a bottom surface of the substrate connection and to have a top exposed surface with through openings extending therefrom through the bottom exposed surface; and creating through vias by applying solder into the through openings, the through vias coplanar with the bottom exposed surface of the encapsulant and coplanar with the top exposed surface of the encapsulant.