Package Structure Overlapping Conductive Portions for Miniaturization
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Solution Overview
Problem
In thin film wafer-level packaging, the limited space in chip packages restricts the number of integrated passive devices, increasing manufacturing costs and package thickness, which hinders miniaturization.
Innovation Solution
A package structure and manufacturing method that includes a redistribution structure with conductive pads and portions, where the first conductive portion overlaps the second conductive portion, and a dielectric layer forms a capacitor, allowing the bottom of integrated passive devices to be manufactured at the same layer as the redistribution structure, reducing costs and increasing manufacturing space.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If integrated passive devices are disposed in the chip package, then the number of devices is limited due to small manufacturing space, but disposing them on the outer surface increases manufacturing cost and package thickness
Solution Approach 1:
The patent utilizes multi-layer stacking architecture where conductive portions are arranged in different layers (first conductive portion in one layer, second conductive portion in another layer). This vertical dimensionality allows integrated passive devices to be formed without occupying lateral manufacturing space, thereby increasing device quantity while maintaining compact package area.
Solution Approach 2:
The patent implements nested arrangement where conductive portions are positioned to overlap each other in the vertical direction (first conductive portion overlaps second conductive portion). This nesting approach allows multiple conductive elements to occupy the same lateral footprint at different heights, maximizing space utilization and enabling more passive devices within the same package area.
2Area of stationary object
If integrated passive devices are disposed on the outer surface of the redistribution structure, then manufacturing cost increases and package thickness increases, but this approach avoids space constraints
Solution Approach 1:
The patent merges the formation of integrated passive devices with the redistribution structure manufacturing process. Both are formed simultaneously in the same fabrication sequence using the same multi-layer stacking and overlapping techniques, eliminating the need for separate post-processing steps and thereby reducing manufacturing cost while controlling package thickness.
Solution Approach 2:
The patent performs preliminary action by forming the conductive portions for integrated passive devices at the same time as the redistribution structure during the initial fabrication process. This preliminary integration avoids subsequent additional processing steps that would increase both cost and thickness, as all conductive elements are established in advance through coordinated multi-layer deposition.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces manufacturing costs and increases the number of integrated passive devices, improving overall device performance by allowing the bottom of passive devices to be manufactured together with the redistribution structure, thus enhancing the package's miniaturization potential.
Implementation Method 1
The first conductive portion, the dielectric layer and the second conductive portion form a capacitor
Data Source
AI summary
A package structure includes a redistribution structure, a first conductive portion, a second conductive portion and a third conductive portion. The redistribution structure includes a first conductive pad and a second conductive pad. The first conductive portion is electrically connected with the first conductive pad. The second conductive portion is electrically connected with the second conductive pad. The first conductive portion at least partially overlaps the second conductive portion. The third conductive portion and the second conductive portion are located at the same layer. The third conductive portion does not overlap any conductive portion which is located at the same layer as the first conductive portion.