3D Package Structure with Overlapping Redistribution Layer Openings
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Solution Overview
Problem
The semiconductor industry faces challenges in achieving high-density integration and reducing parasitic capacitance in three-dimensional (3D) packaging due to limitations in feature size reduction and interconnect performance, which affects signal-to-noise ratio and packaging costs.
Innovation Solution
A method of fabricating a package structure involving a carrier with a buffer layer, a first redistribution layer, and a semiconductor die, where an insulating encapsulant and a second redistribution layer are used to reduce parasitic capacitance by controlling the number and size of metallization layers, and optimizing the openings' width ratio, thereby improving signal-to-noise ratio and reducing costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If feature size is reduced to increase integration density, then more components can be integrated into a given area, but parasitic capacitance increases and signal-to-noise ratio deteriorates
Solution Approach 1:
The patent transitions from two-dimensional planar interconnects to three-dimensional vertical interconnects by stacking multiple metallization layers. This dimensional change allows signal transmission paths to be routed vertically through the package structure, reducing the horizontal trace lengths that contribute to parasitic capacitance while maintaining high integration density.
Solution Approach 2:
The patent divides the interconnect structure into multiple segmented metallization layers (first redistribution layer, second redistribution layer, third redistribution layer) separated by dielectric layers. This segmentation allows each layer to be optimized for specific signal routing functions, reducing cross-layer interference and minimizing parasitic capacitance between adjacent conductors.
2Adaptability or versatility
If more metallization layers are added to improve interconnect performance, then signal routing flexibility increases, but device complexity and manufacturing difficulty increase
Solution Approach 1:
The patent designs each metallization layer to serve multiple functions: the first redistribution layer handles both power delivery and signal routing, the second redistribution layer provides both mechanical support and electrical interconnection, and the third redistribution layer enables both signal transmission and testing access. This multi-functionality reduces the need for additional dedicated layers.
Solution Approach 2:
The patent combines several functions into integrated structures: the sensor die integrates touch sensing electrodes with display functionality, the insulating encapsulant simultaneously provides electrical isolation, mechanical protection, and environmental sealing, and the metallization layers are merged with the substrate structure to eliminate separate interconnect components.
3Productivity
If advanced 3D packaging techniques are implemented to achieve high-density integration, then performance improves, but manufacturing precision requirements increase
Solution Approach 1:
The patent performs preliminary alignment mark formation on the substrate before depositing the first metallization layer. These alignment marks are used throughout the subsequent fabrication process to ensure precise registration of the sensor die, redistribution layers, and other components, thereby reducing the cumulative alignment errors that typically arise in multi-step 3D packaging processes.
Solution Approach 2:
The patent introduces dielectric layers as intermediary structures between the substrate and sensor die, and between successive metallization layers. These dielectric intermediaries provide mechanical tolerance compensation, thermal expansion buffering, and electrical isolation, thereby reducing the stringency of manufacturing precision requirements while maintaining high-density integration.
Data Source
AI summary
A package structure including a semiconductor die, an insulating encapsulant, and a redistribution layer is provided. The semiconductor die includes a semiconductor substrate, a plurality of metallization layers disposed on the semiconductor substrate, and a passivation layer disposed on the plurality of metallization layers. The passivation layer has a first opening that partially expose a topmost layer of the plurality of metallization layers. The insulating encapsulant is encapsulating the semiconductor die. The redistribution layer includes at least a first dielectric layer and a first conductive layer stacked on the first dielectric layer. The first dielectric layer has a second opening that overlaps with the first opening, and a width ratio of the second opening to the first opening is in a range of 2.3:1 to 12:1. The first conductive layer is electrically connected to the topmost layer of the plurality of metallization layers through the first and second openings.