Semiconductor Package Pad Layout for Dual-Speed Testing
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Solution Overview
Problem
Existing semiconductor device package structures face challenges in accommodating both low-speed and high-speed testing requirements, leading to increased test costs and time due to the need for separate probe cards and potential interference from probe marks, while also affecting production cycles and costs.
Innovation Solution
A package structure design that integrates both top metal and RDL openings, utilizing isolation layers with vias and RDLs to create first and second pads for low-speed and high-speed testing, respectively, with offset center points for efficient probe card alignment, reducing the need for multiple probe cards.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If separate probe cards are used for low-speed and high-speed testing, then testing functionality is improved, but test costs and device complexity increase
Solution Approach 1:
The patent creates a universal probe card that can perform both low-speed and high-speed testing functions by designing two sets of pads (first pads for low-speed testing, second pads for high-speed testing) with corresponding RDL paths on the same package structure. This multi-functional design eliminates the need for separate probe cards for different testing scenarios, thereby reducing test costs and device complexity while maintaining comprehensive testing capability.
2Adaptability or versatility
If separate probe cards are used for low-speed and high-speed testing, then testing functionality is improved, but production time increases
Solution Approach 1:
The patent merges the low-speed and high-speed testing capabilities into a single integrated package structure with both first pads and second pads available simultaneously. This allows the testing process to be completed in one step using a single probe card, rather than requiring sequential testing with multiple probe cards, thereby significantly reducing production time while maintaining both testing functionalities.
3Measurement precision
If probe marks interfere with each other, then testing accuracy deteriorates, but using offset center points increases design complexity
Solution Approach 1:
The patent applies asymmetric design by offsetting the center points of the first pads and second pads from each other. This asymmetric positioning ensures that probe marks made during low-speed testing do not interfere with high-speed testing pads and vice versa. The offset configuration is carefully designed to maintain electrical performance while preventing physical interference, thus preserving testing accuracy without requiring overly complex design solutions.
4Adaptability or versatility
If RDL paths are added for high-speed testing, then testing capability is improved, but parasitic capacitance increases
Solution Approach 1:
The patent optimizes the RDL path parameters by controlling the line width, line spacing, and length of the redistribution layer paths connecting the second pads to the interconnection layer. By carefully adjusting these geometric parameters, the design achieves the necessary testing capability while minimizing the parasitic capacitance introduced by the RDL structures. This parameter optimization allows high-speed testing to be performed with acceptable signal integrity.
Data Source
Figure 1~2b
Figure 3a
Figure 3b
AI summary
Embodiments of the present disclosure propose a package structure and a manufacturing method thereof, and a semiconductor device. The package structure includes an isolation layer with multiple vias, N first pads, N Redistribution Layers (RDLs), and a first insulating layer. Each of the vias exposes a respective part of an interconnection layer arranged on a surface of a semiconductor functional structure. Each of the N first pads is formed by a respective part of the interconnection layer exposed by the corresponding via, where N is a positive integer greater than 1. Each RDL covers the isolation layer and is electrically connected to a corresponding one of the N first pads. The first insulating layer covers and exposes part of area of each RDL. The exposed part areas of at least some of the RDLs includes second pads and third pads. The center point of each second pad has the same offset direction and the same offset distance with respect to the center point of the corresponding first pad. The first pads and the second pads are used for testing when the semiconductor functional structure is at different running speeds respectively. The third pads are used for performing function interaction corresponding to the content tested by the second pad.