Semiconductor Package Pad-Hole Interconnect for Crack-Resistant Stacking
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Solution Overview
Problem
The increasing demand for high-capacity, thin, and miniaturized semiconductor devices has led to issues such as cracks and separation defects in conductive structures within package-on-package technology, which affect the reliability of semiconductor packages.
Innovation Solution
A semiconductor package design incorporating a lower redistribution pad with a pad hole and a conductive post, where the pad hole improves bonding strength and allows for the omission of a separate seed metal layer, enhancing the reliability and productivity of the manufacturing process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If package-on-package technology is used to increase device capacity, then the semiconductor device can achieve higher capacity and miniaturization, but cracks and separation defects occur in the conductive structure between stacked packages
Solution Approach 1:
The conductive post is embedded within the molding member, creating a nested structure where the conductive post is surrounded and protected by the molding material. This nesting approach provides mechanical support and stress distribution, preventing cracks and separation defects in the conductive structure during package stacking.
Solution Approach 2:
The invention uses a composite structure combining the conductive post material with the molding member material. The molding member acts as a composite material system that integrates both structural support and conductive function, improving the overall reliability of the stacked package structure.
2Strength
If a separate seed metal layer is added to improve bonding strength, then the bonding strength between conductive post and pad increases, but the manufacturing process complexity and production time increase
Solution Approach 1:
The invention merges the seed metal layer formation with the pad formation process itself. The pad material serves dual purposes: as the electrical connection element and as the seed layer for conductive post formation. This eliminates the need for a separate seed metal layer, reducing manufacturing steps while maintaining bonding strength.
Solution Approach 2:
The pad structure performs multiple functions: it provides electrical connection, serves as the seed layer for electroplating the conductive post, and acts as the bonding interface. This multi-functionality eliminates the need for dedicated seed metal layers, simplifying the manufacturing process.
3Strength
If a separate seed metal layer is added to improve bonding strength, then the bonding strength between conductive post and pad increases, but the production time and productivity decrease
Solution Approach 1:
The pad formation and seed layer formation are merged into a single manufacturing step. The same photolithography and deposition processes that create the pad also create the seed layer, eliminating additional production time and improving overall productivity.
Solution Approach 2:
The pad is formed in advance with the appropriate material composition and thickness to serve as the seed layer. This preliminary action ensures that when the conductive post is subsequently formed, the bonding interface is already prepared, eliminating the need for separate seed layer deposition steps.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The design enhances bonding strength between the conductive post and the redistribution pad, improving the structural stability and reliability of the semiconductor package while maintaining high productivity.
Implementation Method 1
a pad hole extending from an upper surface of the lower redistribution pad toward a lower surface of the lower redistribution pad, and a portion of the conductive post is disposed in the pad hole
Data Source
AI summary
A semiconductor package includes a lower package substrate including a lower redistribution insulation layer and a lower redistribution pattern; a semiconductor chip disposed on the lower package substrate; a molding member disposed on the lower package substrate and covering at least a portion of the semiconductor chip; a conductive post disposed in the molding member; and a lower redistribution pad disposed between the conductive post and the lower redistribution pattern, wherein the lower redistribution pad includes a pad hole extending from an upper surface of the lower redistribution pad toward a lower surface of the lower redistribution pad, and a portion of the conductive post is disposed in the pad hole.