Semiconductor Package Pad Insulation Layout for SMT Short Prevention
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Solution Overview
Problem
During surface mount technology (SMT), solder members on a printed circuit board (PCB) can experience warpage, leading to short circuits at the corners due to the circular shape of solder resist openings, which existing technologies fail to effectively prevent.
Innovation Solution
A semiconductor package design featuring insulation members with specific height configurations around connection pads, where the first insulation member has a higher height than the connection pads and the second insulation member has a lower height, acting as barriers to prevent solder paste flow and guide it away from potential short circuits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a circular solder resist opening is used, then the solder members can be easily formed, but short circuits occur at the corners due to warpage causing solder collapse
Solution Approach 1:
The solder resist opening changes from a conventional circular shape to an asymmetric shape with reduced area at the corner portions. This asymmetric design prevents solder members from expanding circularly and contacting each other at corners during warpage, while still allowing proper solder formation at other locations
Solution Approach 2:
The solder resist opening has different characteristics at different locations: the corner portions have reduced area to prevent short circuits, while other portions maintain normal characteristics for proper solder bonding. This local differentiation resolves the contradiction between ease of manufacture and short circuit prevention
2Reliability
If the solder resist opening area is reduced at corner portions, then short circuits are prevented, but the solder member bonding area is reduced
Solution Approach 1:
The solder resist opening is designed with locally differentiated properties: corner portions have reduced area specifically for short circuit prevention, while non-corner portions maintain sufficient area for reliable solder bonding. This ensures both reliability and adequate bonding area
Data Source
AI summary
A semiconductor structure may include an insulation layer surrounding side surfaces of vias, connection pads on the vias, respectively, a first insulation member on the insulation layer and including through openings in which the connection pads respectively are disposed, and a second insulation member on the insulation layer and surrounding the first insulation member. Each corresponding connection pad among the plurality of connection pads may be on a corresponding via among the plurality of vias and in a corresponding through opening among the plurality of through openings. A height of the second insulation member may be lower than the heights of the connection pads. Outermost through openings among the through openings may include a first inner side surface defined by a side surface of the first insulation member and a second inner side surface defined by a side surface of the second insulation member.