Semiconductor Package Pad Layout Without Probe-Damaging Partition Walls
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing semiconductor device packaging structures face issues with probe card damage and contamination due to partition walls between testing and functional interaction areas, leading to reduced accuracy and reliability.
Innovation Solution
A package structure design with continuous first and second pads on a redistribution layer, eliminating partition walls, and using an insulating layer to protect the redistribution layer and improve positioning accuracy.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If partition walls are provided between testing area and functional interaction area, then area identification is improved, but probe card damage and contamination increase
Solution Approach 1:
The patent removes the partition wall structure between the testing area and functional interaction area. By extracting this harmful element, the probe card can operate without physical obstacles that cause damage and contamination, while area identification is maintained through separate pad structures and positioning methods
Solution Approach 2:
The patent introduces an insulating layer as an intermediary between the redistribution layer and the probe card contact areas. This layer provides electrical isolation and protection without requiring physical partition walls, thereby preventing probe card damage while maintaining area differentiation
2Measurement precision
If partition walls are provided between testing area and functional interaction area, then area identification is improved, but contamination increases
Solution Approach 1:
The patent removes the partition wall structure that generates contamination during probe card operations. By eliminating this physical barrier, the source of contamination is removed while area identification functionality is preserved through alternative means such as pad positioning and insulating layers
Solution Approach 2:
The patent converts the potential harm of having no partition walls (which could lead to contamination) into a benefit by using insulating layers and carefully designed pad structures. This approach eliminates contamination sources while maintaining area differentiation, turning the absence of partition walls into a protective feature
3Reliability
If partition walls are eliminated, then probe card damage is reduced, but area identification becomes more difficult
Solution Approach 1:
The patent introduces insulating layers as intermediary elements that provide area identification and electrical isolation without requiring partition walls. These layers enable the probe card to distinguish between testing and functional interaction areas while maintaining continuous contact surfaces that prevent damage
Solution Approach 2:
The patent applies different properties to different areas: the insulating layer provides electrical isolation and area identification in specific regions, while the redistribution layer provides continuous conductive paths in other areas. This local differentiation enables area identification without requiring physical partition walls
Data Source
Figure 1
Figure 2A
Figure 2B
AI summary
Embodiments of the disclosure provide a packaging structure, a method for manufacturing the same and a semiconductor device. The packaging structure includes a redistribution layer electrically connected with an interconnection layer of a semiconductor functional structure, and an insulating layer covering and exposing part of the redistribution layer. The exposed part of the redistribution layer includes at least one first pad. The first pad includes a first area and a second area arranged continuously. The first area is configured for testing. The second area is configured for performing functional interaction corresponding to content of the test.