Semiconductor Package Pad Layout for Single-Card Multi-Speed Testing
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Solution Overview
Problem
Current semiconductor device packaging structures require separate test pads for low-speed and high-speed testing, leading to increased test costs and time due to the need for two sets of probe cards and potential redistribution layer overextension beyond the semiconductor edges.
Innovation Solution
A package structure with an isolation layer, N first pads, N redistribution layers, a first insulating layer, second pads, and third pads, where the second and third pads have consistent offset positions relative to the first pads, allowing for testing at different speeds with a single set of probe cards and preventing redistribution layer overextension.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If separate test pads for low-speed and high-speed testing are provided, then testing functionality is improved, but test costs and time increase due to requiring two sets of probe cards
Solution Approach 1:
The patent makes the first pads serve multiple functions: they are used for both low-speed testing (directly) and high-speed testing (through redistribution layers that connect to the same pads). This multi-functionality eliminates the need for separate probe cards for different test speeds, reducing test costs and time while maintaining comprehensive testing capability
2Adaptability or versatility
If separate test pads for low-speed and high-speed testing are provided, then testing functionality is improved, but device complexity increases due to requiring two sets of probe cards
Solution Approach 1:
The patent creates a universal test interface where the same first pads and probe cards can be used for both low-speed and high-speed testing. The redistribution layers enable high-speed signals to be routed to the same physical pads, simplifying the test system architecture while maintaining the ability to perform different types of tests
3Ease of operation
If redistribution layers are extended beyond semiconductor edges to accommodate test pads, then pad placement flexibility is improved, but manufacturing precision requirements increase
Solution Approach 1:
The patent resolves the precision issue by utilizing the vertical dimension through multiple redistribution layers at different heights. Instead of extending pads horizontally beyond chip edges (which requires high precision), the solution stacks redistribution layers vertically, with upper layers providing test access while lower layers maintain precise alignment with the semiconductor substrate edges
Data Source
AI summary
A package structure includes N first pads, N redistribution layers, second pads and third pads. Each first pad is formed by a interconnect layer exposed by one via hole. Each redistribution layer covers the isolation layer and is electrically connected with a corresponding first pad. Some first pads are arranged side by side along a first direction near a first edge of the semiconductor functional structure, and other first pads are arranged side by side along the first direction near a second edge of the semiconductor functional structure. The exposed parts of each redistribution layer form a second and a third pad. Both an offset direction and an offset distance between a center point of the second pad and that of a corresponding first pad are same. A relative position between the second pad and the third pad for some redistribution layers is different from that for others.