Package Structure Panel Mounting for Volume Reduction
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Solution Overview
Problem
Current Package On Package (POP) techniques have low efficiency in reducing the volume and thickness of semiconductor chip packages, failing to meet the requirements of miniaturized, portable, ultra-thin, multimedia, and low-cost electronic products.
Innovation Solution
A method involving a pre-packaged panel with multiple semiconductor chips and passive components, mounted on a circuit board with interconnected input and output pads, where metal bumps are used for soldering and a filling layer is formed to create independent package structures, improving packaging efficiency by integrating multiple semiconductor chips and passive components with the circuit board.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If conventional single semiconductor chip package technique is used, then package structure is simple, but volume and thickness cannot be reduced effectively
Solution Approach 1:
The patent implements Package On Package (POP) structure where a second semiconductor chip is mounted on top of a first semiconductor chip, creating a nested vertical stacking configuration. This nesting approach reduces the horizontal footprint and overall package volume while maintaining functional separation of components.
Solution Approach 2:
The patent transitions from traditional horizontal planar packaging to vertical three-dimensional stacking by mounting the second chip on the first chip in the vertical dimension. This dimensional change enables more efficient use of space and reduces package thickness.
2Productivity
If POP technique is used to reduce volume and thickness, then package size is reduced, but packaging efficiency remains low
Solution Approach 1:
The patent applies preliminary encapsulation to the first semiconductor chip before mounting the second chip. The first chip is pre-encapsulated with protective material and its bonding pads are exposed in advance, preparing the structure for subsequent chip mounting and reducing overall packaging process time.
Solution Approach 2:
The patent combines multiple packaging operations into an integrated process where the first chip is encapsulated, the second chip is mounted on it, and additional encapsulation is performed in a coordinated sequence. This merging of steps improves packaging efficiency by reducing the number of separate processing cycles.
3Productivity
If multiple semiconductor chips are packaged together with circuit board, then packaging efficiency is improved, but warping and air gaps may occur
Solution Approach 1:
The patent introduces a filling layer as an intermediary material that fills the space between the stacked semiconductor chips and the circuit board. This filling layer acts as a mediator that prevents warping by distributing mechanical stress and eliminates air gaps that could cause instability or interfere with signal transmission.
Solution Approach 2:
The patent modifies the physical parameters of the package structure by introducing a filling material with appropriate mechanical properties. The filling layer changes the stiffness, thermal expansion characteristics, and stress distribution parameters of the overall package, thereby preventing warping and maintaining structural stability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method enhances packaging efficiency by allowing multiple semiconductor chips and passive components to be packaged together, reducing warping and air gaps, and improving fluidity of the filling material, resulting in a more systematic and efficient package structure compared to single chip packaging.
Implementation Method 1
improving fluidity of the filling material, resulting in a more systematic and efficient package structure
Implementation Method 2
the first metal bumps of the pre-packaged panel and the input pads on the first surface of the circuit board may respectively be soldered together
Data Source
AI summary
A method for forming a package structure is provided, which includes: providing a pre-packaged panel including a first encapsulation layer, which includes multiple integrating units each including at least one semiconductor chip with multiple first pads, and first metal bumps are disposed on the first pads; providing a circuit board including a first surface and a second surface, where the circuit board includes multiple carrying units each including multiple input pads on the first surface and multiple output pads on the second surface; mounting the pre-packaged panel on the first surface to form multiple package units; forming a filling layer by filling a space between the first surface and the pre-packaged panel; forming second metal bumps on the output pads on the second surface; cutting the structure based on the multiple package units to form multiple independent package structures. Accordingly, the package structure improves package efficiency.