Semiconductor Package Structure for More Passive Devices
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Solution Overview
Problem
Current semiconductor packaging methods limit the number of passive devices that can be included and involve a complex and costly silicon via process.
Innovation Solution
A package structure and packaging method that involve a substrate with first and second surfaces, passive devices mounted on the first surface, a first chip mounted on the second surface, and metal connection structures that electrically connect the chip to the substrate, simplifying the interconnection process and reducing costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If passive devices are placed on the back face of the semiconductor chip, then electrical connection is achieved, but the number of passive devices is limited and the process becomes complex and costly
Solution Approach 1:
The patent transitions from placing passive devices on the back face (two-dimensional surface) to mounting them on the substrate (another dimensional plane), enabling significantly more devices to be integrated without increasing chip area usage. This dimensional shift resolves the limitation on the number of passive devices while simplifying the interconnection process.
2Reliability
If silicon via process is used to electrically connect chip and passive devices, then electrical connection is achieved, but the process becomes complex and costly
Solution Approach 1:
The patent divides the interconnection function into separate components: the substrate provides connection terminals that electrically connect to both the passive devices and the chip. This segmentation eliminates the need for complex silicon via processes while maintaining reliable electrical connections through simpler, more cost-effective means.
3Quantity of substance
If passive devices are mounted on the substrate, then the number of passive devices is increased, but substrate area is consumed
Solution Approach 1:
By mounting passive devices on the substrate rather than on the chip, the patent utilizes the substrate's larger area and different spatial arrangement, allowing more devices to be accommodated without compromising chip area efficiency. The substrate serves as an extended platform that provides both mechanical support and electrical interconnection.
Data Source
AI summary
The present disclosure relates to a package structure and a method for forming the same. The package structure includes: a first surface and a second surface that are opposite, passive devices mounted on the first surface of the substrate; a first molding layer encapsulating the passive devices and covering the first surface of the substrate; a first chip comprising a back face and a functional face that are opposite; metal connection structures each comprising a horizontal metal strip and a vertical metal pin electrically connected to the horizontal metal strip; a second molding layer encapsulating the metal connection structures and the first chip and covering the second surface of the substrate; and first solder bumps on the exposed top surfaces of the external terminals.