Semiconductor Package Structure With Pillar Height Compensation
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Solution Overview
Problem
The semiconductor industry faces challenges in integrating semiconductor devices with varying heights onto a common package structure, leading to height differences that complicate planarization processes and require additional steps for leveling, which can increase costs and reduce manufacturing efficiency.
Innovation Solution
The use of pillar structures with varying heights mounted onto semiconductor devices to compensate for height differences, followed by a planarization process that removes portions of both the encapsulant and pillar structures, allowing for the creation of a uniform surface and facilitating the integration of these devices onto a redistribution layer (RDL) structure.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If additional leveling steps are used to compensate for height differences, then manufacturing precision is improved, but device complexity and manufacturing time increase
Solution Approach 1:
Pillar structures are formed on semiconductor devices before packaging to pre-compensate for height differences. This preliminary action eliminates the need for post-packaging leveling steps, as the height compensation is already in place before the devices are integrated into the final package structure.
Solution Approach 2:
The height compensation function is extracted from the packaging process and implemented separately on the semiconductor devices themselves through pillar structures. This separates the height adjustment step from the packaging process, allowing each to be optimized independently and eliminating redundant operations.
2Manufacturing precision
If pillar structures are used to compensate height differences, then manufacturing precision is improved, but the number of manufacturing steps increases
Solution Approach 1:
The pillar formation process is merged with the existing semiconductor device fabrication process, utilizing the same deposition and patterning equipment and materials already present in the manufacturing line. This integration allows height compensation to be achieved without adding separate manufacturing steps or extending the production cycle.
3Shape
If planarization removes portions of pillar structures, then surface uniformity is improved, but material is removed and device complexity increases
Solution Approach 1:
The pillar structures are designed with locally optimized dimensions and materials tailored to the specific height compensation needs of each semiconductor device. This localized approach ensures that only the necessary amount of material is present at each location, minimizing waste during planarization while achieving the required surface flatness.
Data Source
AI summary
A package structure includes a semiconductor device including a conductive feature, a joint layer, a pillar structure, an encapsulant and a RDL structure. The joint layer is disposed on the conductive feature. The pillar structure is disposed on and coupled to the semiconductor device through the joint layer. The encapsulant laterally encapsulates the semiconductor device and the pillar structure. The RDL structure is electrically connected to the semiconductor device.